CMOD S6 FPGA start-up

[OLucia]

We are intensive users of CMOD S6 FPGA in our power electronics design. During start-up (programming from FLASH), some outputs acquire random values, and may accidentally short-circuit the power converter, leading to the converter destruction. Is there any way to pull down the FPGA outputs during the start-up process in the CMOD S6 board?

Thanks,

[xc6lx45]

Hi,

see table 2.6 https://www.xilinx.com/support/documentation/user_guides/ug380.pdf page 41 "HSWAPEN"

As I understand, it is pulled low by R49 https://reference.digilentinc.com/_media/cmod_s6:cmods6_sch.pdf page 3.

So there is weak pull-up enabled generally.

Removing R49 should disable the general pullup, HSWAPEN is pulled high internally (see Table 5.2).

See also this discussion:

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-FPGA-IO-state-before-configuration/td-p/259300

As a result, your pins will be floating. If hi-Z is insufficient for safe operation (likely), you have to use external pullup-/down resistors to force them to a safe state.