I'm just...so lost (shift register)

[qasddd]

Currently I'm trying to implement a shift register with a clock divider (to blink leds one by one in a row). To begin, I'm sorry. I know this code is not super hot. I'm very new to pretty much everything related to fpgas (embedded systems, verilog, coding in general)  

So, I am...very lost. This is what I've been able to put together so far. I'm pretty ok with the D flip-flop and clock divider (these work in simulation), but the shift register? I'm not even sure if I'm going about it right. Simulation runs but the led output is all the same, and thats no good. 

So, what am I doing wrong? 

 

D flip-flop:
    module d_ff(
        input D,
        input clk,
        input rst,
        output reg Q
        );
    
        always @ (posedge (clk),posedge (rst))
        begin
            if (rst == 1)
                Q = 8'd1;
            else
                Q = D;
        end    
          
    endmodule

Clock divider:

module clk_divider(
    input rst,
    input clk,
    output Q
    );
    
wire [26:0] din;
wire [26:0] clkdiv;

d_ff d_ff0 (
    .clk(clk),
    .rst(rst),
    .D(din[0]),
    .Q(clkdiv[0])
);

genvar i;

generate
for(i = 1; i<27; i=i+1)
begin : d_ff_gen_label
    d_ff d_ff_inst (
        .clk(clkdiv[i-1]),
        .rst(rst),
        .D(din[i]),
        .Q(clkdiv[i])
);
end
endgenerate;

assign din = ~clkdiv;
assign Q = clkdiv[26];

endmodule

Shifter:

module shift_reg(
    input En,
    input rst,
    output [7:0] led
    );

//connector wire between flipflops
wire [7:0] bitshift;

// creating the shifter out of d flipflops

//1st one
d_ff d_ff0(
    .D(bitshift[0]),
    .clk(En),
    .rst(rst),
    .Q(bitshift[1])
);

//middle ones
genvar i;
generate
for (i=1; i<7; i=i+1)
begin : d_ff_gen_label0
    d_ff d_ff_inst1(
        .clk(En),
        .rst(rst),
        .D(bitshift[i]),
        .Q(bitshift[i+1])
    );
    end
endgenerate;
    
//last one
d_ff d_ff1(
    .clk(En),
    .rst(rst),
    .D(bitshift[7]),
    .Q(bitshift[0])
);
    
assign led = bitshift;

endmodule

wrapper code:

module wrapper(
    input rst,
    input clk,
    output [7:0]led
    );

wire clk_connector;

clk_divider clk_div1(
    .rst(rst),
    .clk(clk),
    .Q(clk_connector)
);

shift_reg shiftreg1(
    .En(clk_connector),
    .rst(rst),
    .Q(led)
);

endmodule

 

[artvvb]

Hi qasddd,

So the issue that I can see right now is that all of the DFFs in your shifter reset to a logic high, and the only other value Q can receive is D, which is its neighbors Q. So if all eight DFFs are already high, and can only become what their neighbor already is, there is no way for any of them to go low. There are several ways to solve this, you seem to currently be writing your code in a structural style, where each module does very little, but they are connected together in complicated ways -- and this is a perfectly valid way of going about things, it can just be a little confusing to read at times. The most straightforward way to fix the "all leds are high"  problem, and stay in style, would be to define a second version of the d_ff module which resets low, allowing you to control which leds are initially high.

The way that the d_ff module is being reset reads in a somewhat confusing way. Since Q is a one-bit register, it is only being set by the least significant bit of the eight bit number you are assigning into it. The following might help a little:

if (rst == 1)
    Q = 8'd1;

is functionally equivalent to:

if (rst == 1)
    Q = 'b1;

Thanks,

Arthur

[Alex]

Hi, when you have reset, I guess you want to set the logic low. However, you put one in the reset. And thinking about your design, you want to shift one bit from led0 (q0) to ledx (qx). This means when reset is not 1, you want to move the bit in q0 move to q1. Then in the next positive edge, you want the bit moving from q1 to q2. Then next is q2 to q3. Based on this logic, you can model the behavior. I guess you are using d flip flop to create clock divider. Perhaps you can refer to learn.digilentinc.com. There are some verilog example code for clock divider and shift register.