qasddd Posted January 14, 2016 Share Posted January 14, 2016 Hello! I'm self-teaching myself how to program and use FPGA's, and I'm using the learn digilent digital projects as part of this endeavor. I've made it past digital project 5 (multiplexer, decoder, encoder, and shifter) just fine. BUT in project 6 (hierarchical design in verilog) I'm having some issues. The thing is, project 5 had us code these different circuits using arrays, which are NOT used in project 6. The input/output organization is different, and its just very confusing for a beginner, which these tutorials are aimed for. If someone has any example code for project 6, I would love to have a look at it. I know once I see how its done it'll be easy, but for now I'm struggling a fair amount. Also, as an extra bonus point question, is there any way to assign multiple parts of an array to different constants in a case statement? Like: case (I) 2'b0: Y[0] = 4'b0; Y[1] = 4'b1; but that won't give me an error message? or is this just not possible? Link to comment Share on other sites More sharing options...
Commanderfranz Posted January 20, 2016 Share Posted January 20, 2016 Hi qasddd, Regarding your second question, you can. If you use multiple lines in an if or case statement you need to inclose them in a begin, end structure. For example, case (I) 2'b0: begin Y[0] = 4'b0; Y[1] = 4'b1; end Alternatively you can assign both of those values in the same line Y = 2'b10; assuming Y is only two bits wide. However in your example you are assigning a 4 bit constant to a 1 bit value, which will give you warnings. When you say Y[0] you are saying the 0th bit of Y. So that is only one bit wide. Regarding your second question, I'm not sure what part of project 6 you are having trouble with, you are going to need to be more specific. Link to comment Share on other sites More sharing options...
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