A small question. I need to generate a signal of 28.8MHz (sine wave), so in FPGA I've build a DDS and it's generating a nice sine wave @ 27.799MHz (close enough :p). For connecting this to a certain target board I've bought the PMOD DA3 (https://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/). There is only one small problem that I can't figure out...
I know when you're sampling you have to comply to Shannon's theory, but how is it with DACs when you are reconstructing a signal, do they also have to comply to this? I've dived into the schematic of the PMOD DA3 and saw that a chip from Analog Devices is used, more specific the AD5541A. When looking into the datasheet, I saw that it connects with a 50-MHz SPI-/QPSI-/... interface, meaning that SCLK can take a maximum of 50MHz when a voltage supply of 2.7 - 5.5V is applied...
Now the question that I have is, does a DAC need to comply to Shannon's theorem, meaning that the absolute max I can generate with this DAC is a 25MHz signal (in ideal conditions), or does a DAC not have to comply with this and I can just generate the signal without any problem :)?
Question
tommienator
Hey everybody,
A small question. I need to generate a signal of 28.8MHz (sine wave), so in FPGA I've build a DDS and it's generating a nice sine wave @ 27.799MHz (close enough :p). For connecting this to a certain target board I've bought the PMOD DA3 (https://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/). There is only one small problem that I can't figure out...
I know when you're sampling you have to comply to Shannon's theory, but how is it with DACs when you are reconstructing a signal, do they also have to comply to this? I've dived into the schematic of the PMOD DA3 and saw that a chip from Analog Devices is used, more specific the AD5541A. When looking into the datasheet, I saw that it connects with a 50-MHz SPI-/QPSI-/... interface, meaning that SCLK can take a maximum of 50MHz when a voltage supply of 2.7 - 5.5V is applied...
Now the question that I have is, does a DAC need to comply to Shannon's theorem, meaning that the absolute max I can generate with this DAC is a 25MHz signal (in ideal conditions), or does a DAC not have to comply with this and I can just generate the signal without any problem :)?
Thank you :)!
Link to comment
Share on other sites
1 answer to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.