Basys2 Ucf File Produces Many Errors

hib · November 23, 2014

I am attempting to generate a bit file for the sample project on the Learn.Digilent site: "Design Simple Logic Circuit Project 3: Guess the Logic". when I use the Digilent Basys2 UCF file from the Diglient website I get a huge number or errors (see attached text file). The errors all are related to missing design objects in the UCF file. How can I solve this problem?

error_UCF.txt

basys2board.ucf.rtf

hamster · November 24, 2014

thanks but those are the values I used. I spent many hours entering the sample code from your book and others, with little success.

I am going to give FPGAs a long rest.

Don't give up just yet - just try replacing

NET "ld[1]" LOC = "p14" ;

with

NET "ld<1>" LOC = "M11";

And see if one of your errors goes away! The reason is that the Basys2 doesn't have a pin named P14.... that signal is connected to the pin named M11.

hamster · November 23, 2014

ERROR:MapLib:30 - LOC constraint P14 on ld<1> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

ERROR:MapLib:30 - LOC constraint P36 on sw<1> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

ERROR:MapLib:30 - LOC constraint P29 on sw<2> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

ERROR:MapLib:30 - LOC constraint P24 on sw<3> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

ERROR:MapLib:30 - LOC constraint P15 on ld<0> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

ERROR:MapLib:30 - LOC constraint P38 on sw<0> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

The most likely cause for this is that you have the wrong device and/or package selected for your FPGA board.

Right-click on the top level of your project and select properties. Make sure that the Device Is XC3S100E or XC3S250E and that the package is set to CP132.

It should look something like

If this doesn't fix it, can you post a screenshot of your design's properties?

hamster · November 23, 2014

Comment out or delete all the unused lines - you should only have those that your design uses.

There is a synthesis option that makes these errors into warnings , but if you use it you will regret it! You will spend a night trying to track why a design does work only to find a signal called 'LEDs' in you HDL is called 'LED' in your UCF file, and a warning has been trying to tell you that all night.

hib · November 23, 2014

I get the same errors with a highly reduced ucf file.

First, here is the Verilog code

module top (

input [7:0] sw,

output [2:0] ld

);

assign ld[1] = (~sw[3] & ~sw[2] & ~sw[1]) | (~sw[3] & sw[2] & sw[1]) | (sw[3] & ~sw[2] & sw[1]);

endmodule

--------------

here is the ucf file

NET "ld[1]" LOC = "p14" ;

NET "ld[0]" LOC = "p15" ;

# Pin assignment for slide switches

NET "sw[3]" LOC = "p24";

NET "sw[2]" LOC = "p29";

NET "sw[1]" LOC = "p36";

NET "sw[0]" LOC = "p38";

---------------------------

also tried this ucf file:

NET "ld<1>" LOC = "p14" ;

NET "ld<0>" LOC = "p15" ;

# Pin assignment for slide switches

NET "sw<3>" LOC = "p24";

NET "sw<2>" LOC = "p29";

NET "sw<1>" LOC = "p36";

NET "sw<0>" LOC = "p38";

------------ here are the error messages

..

ERROR:MapLib:30 - LOC constraint P14 on ld<1> is invalid: No such site on the