kunearth Posted November 9, 2015 Share Posted November 9, 2015 Hi: I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL. So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it. For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator? Thanks. Link to comment Share on other sites More sharing options...
TommyK Posted December 1, 2015 Share Posted December 1, 2015 Hi there, I want to start off by saying this project is incredibly advanced and is very difficult to do without using Microblaze and the libraries it supplies. But yes, you would need to use a clock generator to generate a 125 MHz clock for the Ethernet MAC core. Link to comment Share on other sites More sharing options...
mwagner Posted July 13, 2016 Share Posted July 13, 2016 I tried that too, but failed. It was reported it was easier to use the ETH PHY without a MAC at least when UDP is desired. Link to comment Share on other sites More sharing options...
Question
kunearth
Hi:
I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL.
So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it.
For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator?
Thanks.
Link to comment
Share on other sites
2 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.