DDR3 Artix-7 Multiport Native Interface Memory Controller

[ASMartin]

Hi,

I'm looking for information about implementing DDR3 Multiport memory controller with native (not AXI4) interface, maybe any IP Core on ISE or Vivado like DDR2 on Atlys.

No information regarding this issue, except xapp789 or xapp1164 which describes how to create a AXI4 Multiport interface.

VHDL preferred.

Regards.

[mindcircus]

Hello,

There isn't any plug 'n' play IP core that can do this for you. MIG's GUI can generate either AXI or UI interfaces. If you want to use the native interface you have to build the MIG core in Vivado using the memory parameters you want and then find the source files (in verilog, not VHDL) that were automatically generated by the GUI. The next step is to customize the core (throw away the UI block and change the top entity in order to have the native interface ports) and repackage it. This way you will end up with a custom DDR3 controller with native interface. You actually keep only the physical layer of the controller, so you have to build the logic that generates the commands that the user wants to send to the memory.

If you insist on multiport logic, you also have to build an arbiter which will handle the requests from your master logic and translate them into DDR3 commands (refer to JEDEC DDR3 specification). It will really help you if you study the UI block in order to understand how to do it yourself from the beginning...

I have to warn you that this is a quite difficult project, because you have to fully understand MIG's functionality in order to rebuild it the way you want. If you haven't done it yet, refer to UG586 and after that to AR# 51204.

Good luck!

PS. Are you sure that UI interface is not enough for you? You are going to save a lot of effort if you don't touch MIG's internals...

 

Edit: Sorry, its been a long time since I studied MIG.... The native interface is before the Memory Controller so you don't have to implement the DDR3 commands as I write above (you don't have to read AR# 51204 either). It is easier to use the UI interface anyway, since you won't have to change anything inside MIG source code and you can use the flat address space instead of memory's bank, row and column addresses.

[ASMartin]

Hello,

There isn't any plug 'n' play IP core that can do this for you. MIG's GUI can generate either AXI or UI interfaces. If you want to use the native interface you have to build the MIG core in Vivado using the memory parameters you want and then find the source files (in verilog, not VHDL) that were automatically generated by the GUI. The next step is to customize the core (throw away the UI block and change the top entity in order to have the native interface ports) and repackage it. This way you will end up with a custom DDR3 controller with native interface. You actually keep only the physical layer of the controller, so you have to build the logic that generates the commands that the user wants to send to the memory.

If you insist on multiport logic, you also have to build an arbiter which will handle the requests from your master logic and translate them into DDR3 commands (refer to JEDEC DDR3 specification). It will really help you if you study the UI block in order to understand how to do it yourself from the beginning...

I have to warn you that this is a quite difficult project, because you have to fully understand MIG's functionality in order to rebuild it the way you want. If you haven't done it yet, refer to UG586 and after that to AR# 51204.

Good luck!

PS. Are you sure that UI interface is not enough for you? You are going to save a lot of effort if you don't touch MIG's internals...

 

Edit: Sorry, its been a long time since I studied MIG.... The native interface is before the Memory Controller so you don't have to implement the DDR3 commands as I write above (you don't have to read AR# 51204 either). It is easier to use the UI interface anyway, since you won't have to change anything inside MIG source code and you can use the flat address space instead of memory's bank, row and column addresses.

Well, I tried UI but it shows only 1 port, and I need 3 concurrent (fifo buffered) ports at least.

Thanks for your advice and support.

Regards

[mindcircus]

There is not a ready solution for what you are looking for. I can't remember anything in ISE either. You have to build yourself an IP core which will have 3 input ports, it will place the requests inside three FIFOs and a control logic (FSM/Arbiter) that will multiplex them into one output port. You can use a round robin scheme in this logic which will look the empty flag of each FIFO and will pass the request to the output. The three input FIFOs are logical; I think you are going to need one for data and one for commands for each input port.

I don't know your experience on VHDL, but it is not as hard as you think. Of course you are right to look for a ready IP core first...

[ASMartin]

Yeap, that's the right solution, the one provided with DDR2 for 6 family by MIG. I have to implement 3 queues with FIFOs and a round-robin mechanism to access them. I know, but I'm looking for a working solution to save time.

I've been working with ATLYS (Spartan 6) with vmodcam and HDMI output (HD720p split) and some algorithms to enhance borders and color mapping just for a stereovision system, but I need more slices

I already designed and implemented a card to interface FMC to VHDCI (VmodCAM interface). And I'm now mapping the example for VmodCAM from Atlys to Nexys Video, just for testing purposes (I need to sve time just for testing). But IP core for 7 family is quite different and does not provide with 3 ports I need. I translated buffers, clock manager and so on, but memory interface is different.

Thanks a lot for your support.

Regards.

[mwagner]

I also need to move a design from former Spartan 6 to now Artix7 and stumbled over this issue. The core cannot be upgraded and there is no multiport option for Artix designs with native Interface.