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creat counter ip in vivado (vhdl code)


bahare

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hi

i created a counter ip and i use vhdl language, how i can connect my output ip counter to output my master ip in VHDL code ?? for example in below tutorial

http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivad...

after add component and add port map , “reg_data_out <= slv_reg1;” replace with “reg_data_out <= multiplier_out;" in “my_multiplier_v1_0_S00_AXI_inst” file , i want to know what shoud change in “my_counter_v1_0_M00_AXI_VHDL” file after add component above 'begin' and add port map in 'user add logic' ?

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