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coldfiremc

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Posts posted by coldfiremc

    A Guide to Using DDR in the all HDL Design Flow

    in Tutorials

    Posted

    Thanks @zygot. I have two nexys video boards and a Nexys A7 among other fancy RFSoC boards. I would like to follow this test designs. I have a Xilinx enterprise license, so I can open cases, and I use this MIG ip's too much in kind of critical applications to let nasty bugs to appear this way. If you can narrow those bugs, I would get some sort of official answer with Xilinx.
    One of the causes of the limited clocks for MIG is the fact that MIG generates inside its refclock and max PLL clock and divider options get very limited this way. Better designs use 2 clocks: one for data, and one for reference, coming from external oscillators. It would be neat to have more boards designed with 2 differential oscillators (can be cheap oscillators, there's no need to get oven controlled PLL's in domestic boards like digilent's)

    Black screen problem in HDMI passthrough on ZYBO z7-20

    in FPGA

    Posted

    On 1/16/2022 at 9:44 AM, samokami said:

    Hello everyone,

    i am trying to make an HDMI passthrough but i get only a blackscreen. Any idea why?

    the camera used is Sony action cam HDR- as200v res 720p, 24p, tcout mp4, and connected to ZYBO HDMI RX. Output from ZYBO HDMI TX to TV.

    all settings are in attachment

    constant0 st set on 0 value.

    constant1 is set on 1 value.

    thank you in advance.

    HDMIPass.JPG

    Clockwizard.JPG

    clockwizard200MHz.JPG

    constrain.JPG

    DVItoRGB.JPG

    RGBtoDVI.JPG

    Check logs and implemented design to see if the block is optimized/deleted in some way

    Placement problems with DVI to RGB IP

    in FPGA

    Posted

    Ok I found something Interesting

    Despite the board file has the I/O pins defined for this interface (and an associated IP), Implementation fails because i/o pins are not fixed. This is very strange considering that to assign a pin explicitly is enough to fix the I/O mapping.

    421080336_Screenshotfrom2022-01-1011-20-26.thumb.png.eb9d7568b92088ff2a94b94931745510.png

    This is the error (The ISERDES needs an explicit and fixed mapping)

    Here's the "anomaly"1914234798_Screenshotfrom2022-01-1011-22-02.thumb.png.55e352b177498abfe0c8be709f601125.png

    I will check this further, digging in the Board File. Probably it needs a little fix

    Greetings

    Placement problems with DVI to RGB IP

    in FPGA

    Posted · Edited by coldfiremc

    On 10/11/2021 at 6:50 AM, elodg said:

    It look like you board flow interfaces are not picked up. Dig further.

    After developing a project with this board I noticed that this problem is not only affecting the DVI input IP, but also the clock wizards. Apparently the board file has some inconsistent names. Also the constraints for this IP are a little "Weak" and with a minimum modification, are not applied correctly. Please update the board files. A workaround for this is write constraints manually, but this is not always easy for block designs.

    Also there's other problem with rgb to DVI, input frequency is not updated accordingly, so this error appears

    [BD 41-927] Following properties on pin /rgb2dvi_0/PixelClk have been updated from connected ip, but BD cell '/rgb2dvi_0' does not accept parameter changes, so they may not be synchronized with cell properties:
        FREQ_HZ = 75000000 
    Please resolve any mismatches by directly setting properties on BD cell </rgb2dvi_0> to completely resolve these warnings.

    Also incorporating the clock generator inside the ip limit the IP seriously. I think that the integrated clock generator must be discarded to simplify design and allow proper clock settings.
     

    Placement problems with DVI to RGB IP

    in FPGA

    Posted

    Hi

    I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good.
    I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong?

    The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo.

    Thanks

     

    Screenshot from 2021-10-03 23-05-29.png

    Does Digilent RGB to DVI support interlaced video ?

    in Embedded Linux

    Posted

    On 7/19/2021 at 4:54 AM, chaitusvk said:

    Thank you 

    RGB to DVI is just about the physical interface and not the video signal itself. AXI4-to-video IP in fact supports interlaced video. The important part is to calculate properly the timings and setting a proper serial clock for HDMI with an external clock manager. You have to check if your FPGA has enough resources to do this, knowing that HDMI serial clock is a little high. 

    Interface ADS4225EVM FMC LPC Board

    in Add-on Boards

    Posted

    Hi

    I have to interface an ADC for a project, and this ADC(ADS4225) fits the requirements. I'm planning to buy the development board and the needed adapter to connect it to the FMC port of a Nexys Video. However, I never interfaced a high speed DDR LVDS device before, and this device (and all of its class) need some signal adjustments to get the data links properly aligned.

    Can I get some guidance to implement input delays and DDR clock calibration?

    Thanks

    Nexys Video HDMI

    in FPGA

    Posted

    39 minutes ago, Mario875 said:

    Thanks for all the info, seems that if I want proper timings at 1080p, 60Hz, 24-bit colour I am best just using the ADV7513 (or similar). Considering the IC's are only £14 from RS Components and they are purpose built for the job, it seems going that route is first of all, less headache and second of all, likely to yield superior results. Not to mention the cost saving vs a Genesys 2! Just need to make up a custom PCB so it can interface to the FPGA via the FMC connector, not a big deal.

     

    As for the Geneys 2, I cannot justify an extra £600 over the Nexys Video, it's just not worth it, even future projects I have involving FPGA's are likely to require lesser devices than the Nexys Video, probably stuff I can do with my current Basys 3. Maybe in future I can re-visit the Genesys, but not just now.

     

    However I might re-visit this topic after I get everything fully functional with my project and have completed boards made up and the project is all but finished. Just to see how well I can make it run without the ADV7513 for my own curiosity.

     

    Seems that the Nexys Video should be able to do 720p & 1080i at 60Hz with 24-bit colour without too much hassle, even 1080p 30Hz with 24-bit colour depth should be fine, but getting it up to 1080p, 60Hz & 24-bit colour I think will have her running a bit hot.

     

    Thanks for all the info so far, especially that IP core! Really good to have that, but I think the answer as to "how did Digilent do it on their demo" (for anyone who finds this thread in the future) is that if they are indeed outputting 24-bit colour, then the only solution has to be running the FPGA out of spec and effectively over-clock it.

    I think that this could be a better approach. However, if you want a more clean board you can buy one of those Trenz Electronik SOM's and snap it in a sort of motherboard for your application. With nexys video you can develop the inner parts of the system and then go for the final model with some of those SOM's. This is in the pricey side, but you will end with a more professional "workflow" and a cleaner product. Also SOM's are cheaper than development boards because the absence of connectors and peripherals.

    Nexys Video HDMI

    in FPGA

    Posted

    It's clear that this cannot be "sufficiently safe" for a commercial design, even considering that the high clock is going into the OSERDESE2. It would be great to hear an "official" answer from Digilent. It's also obvious that clocks in this board are some sort of limited by size/cost/application.Also It's worth to note that the OSERDESE2 implementation is using DDR, that's a pretty neat trick to get the objective frequencies, especially considering the serial clock.

    Most of this pricepoint boards can't even get 720p running with standard timings. This board struggles to get it, bug it gets, and for most developers it's just enough to develop the rest of the system.

    This is a good enough board for the price, and does not rely in jerry-rigged designs or obscure files. I have did lots of high bandwidth stuff just with RTL and board files are quite simple. I'm cleaning the bd to get it on github to upload it and discuss it.

    Nexys Video HDMI

    in FPGA

    Posted

    Download "vivado-library" and the constraints repo. Nexys video has its own ip to get hdmi output based on oserdese2, its source code is available in the IP itself. It's called "rgb to DVI". It's enough to get 1080p withut problems. You have to put a clock wizard with pixel and serial clocks to make it flexible for any hdmi or DVI mode. I Have a "bare bones" design to get video from hdmi with that. I will upload it to my repo soon

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