zygot

We've updated our procedures to ensure that the modules will be easily identifiable whenever a change to form, fit, or function is made. There will also be a PCN issued before new modules go into distribution.

Hmmm... thanks for the information, you just won me a lunch bet. Perhaps you can answer this question. Why is it that people who have time to engage in unproductive nonsense can't use the time to provide useful help.
Here's a suggestion. Instead of posting snarky remarks, just paste one of your AXI master Verilog source files here with a brief description of how you used it. That can't take up much of your valuable time and could help the average user grasp the topic.

Well, I'll offer one way, which is how I do ZYNQ designs. After creating the board design and generating the output products I tell Vivado to create a wrapper file in the project HDL, typically for me in VHDL. This wrapper then gets instantiated into my own toplevel entity where I can connect to any exposed signals that were made external in the board design. Usually, Vivado attaches IO buffers to these signals but will remove them and spit out warnings that can be ignored. You can look over an example here: https://forum.digilentinc.com/topic/20299-fun-with-phasors/
So, in your schematic above the first thing to do is make your UART signals external...
[edit] I forgot a sentence that I always add: When you have Vivado create your wrapper file make sure to de-select the default option that lets Vivado manage the wrapper code. You want to manage this to avoid unnecessary fights with the tools.

The Spartan 3 family is not supported by any version of Vivado. You will have to use ISE. I have a vague recollection that the last version of ISE available in the Xilinx archives doesn't support all of the Spartan 3 devices either so you will have to do a bit of research. The last ISE 14.7 distributed by Xilinx did support you device.
 

Stay tuned to the Project Vault forum. Now that Digilent lets me play with well designed modules that do conversion between the analog and digital realms with a reasonable bandwidth on Xilinx hardware there are all sorts of fun ideas to explore.

Hi  @abd,
Part of the CMODA35T demo was indeed integrated into an IP form. The source for that code is not currently in a release form. The objective of the demo is to provide an alternate, quick and painless way for individuals new to the Xilinx toolset to create a bitstream and see their new CMOD-A35T working. Please understand that there aren't many people getting paid to provide code or assistance around here; so there's that pesky trade-off of providing something for free and providing something intended to better the "community".
The more important purpose of the demo is to encourage users to try developing their VHDL skills; so providing a bit of motivation to have them design their own functionality isn't a bad thing from my perspective. There is plenty of HDL source available in the Digilent Project Vault to assist in this process. Of course, there are also a number of people willing to help with specific questions on this forum as well.
I realise that developing you own code base ( IP if you will ) is a daunting task for those getting started and using the development methods that Xilinx and Digilent prefer appear to be an easier short cut to working designs. I'm encouraging the longer, more difficult, path because I believe that the destination is a much better place to operate in. There are other forums within the Digilent ecosystem that offer a discussion of ideas and might be interesting or even perhaps useful.
I do thank you for mentioning that you tried out the demo. I have been encouraged to submit new projects to the Vault and always try to allow users to expand on the project's limited objectives by re-using source. 

CmodA735tDemo is a Vivado project that requires very little resources and is an easy way to try out the board's resources.
Requires Vivado 2015.2 or later and a Cmod A7-35T board. There is a Python program to run the demo that also requires Python 2.7 and pyserial 2.7 but any terminal emulation program such as Putty will also work, though with a bit more effort.
CmodA735tDemoR1.zip
NOTE: Vivado 2019.2 and later breaks the Vivado IP created in earlier versions. To build this project in Vivado 2019.2 just follow the README file except instead of adding the clk_wiz_0.xci file as IP you need to create an MMCM using the Vivado 2019.2 clock Wizard (use the default name) . The only thing that needs to be changed from the default settings is the input clock rate which is 12 MHz. I use the archive above from here to build the project just today using Vivado 2019.2 on WIN10.