I did a git checkout v2017.4 and re-generated the Vivado project in 2017.4. It asked for IP upgrade and I had to create a wrapper for the block design manually (which I should not have had to do), but Synthesis and Implementation worked.
Could you try the 2018.2 release too in Vivado 2018.2 and see if it works.
Removing debug logic of pcam-5c reference design
in FPGA
Posted
I did a git checkout v2017.4 and re-generated the Vivado project in 2017.4. It asked for IP upgrade and I had to create a wrapper for the block design manually (which I should not have had to do), but Synthesis and Implementation worked.
Could you try the 2018.2 release too in Vivado 2018.2 and see if it works.