[PS PL communication using BRAM for sending 30 bytes of data in intervals]

On 4/13/2024 at 2:01 AM, artvvb said:

Hi @pepeok

So I'm not sure about AXI BRAM, it may be possible, but I recall running into some issues (quite some time ago) with trying to control the same AXI BRAM from an HDL module and by PS through an AXI BRAM controller at the same time. If going this route, I'd assume the AXI BRAM would be configured as a true dual-port RAM. Using an AXI interface to write to block RAM is still a good approach though - I'm just not sure about how well the IP in block design would handle the use case. The first lab in this series might help if you're using this approach though - it at least shows wiring up the PS -> BRAM part of this communication path: https://digilent.com/reference/programmable-logic/arty-z7/intro-to-fpga.

200 ms is plenty of time for any number of different interfaces. Controlling a custom module with an AXI GPIO ought to work, though you need a way for the module you're controlling to tell when new data is available - using a second GPIO channel to toggle a bit back and forth whenever new data is available on the first GPIO channel would work fine.

Hope this helps,

Arthur

Hello @artvvb thanks for your answer! So in order for this to work i have to complete the PS to BRAM and then the AXI GPIO to control the flag?

I don't really care about specs etc :P Is this the easiest approach? How would you approach a problem like this? 

I'm just trying to figure it out. Thanks for your time!!!

[PS PL communication using BRAM for sending 30 bytes of data in intervals]

Hello everyone, I'm new to the FPGA world and i want to create a simple project where i send data from the ARM to the FPGA on a Zynq board (arty z7-20).

I want to send 30 bytes every 200ms to the FPGA and make a very simple calculation like add two values or something to let me know the FPGA got the correct data. 

I've set up an echo server project using FREERTOS and i receive tcp packets via ethernet and I parse them. I then want to send to the FPGA (for start every 200ms) and i want to know if the FPGA got the correct data.

I've seen examples of PS PL communication but the amount of interfaces confuses me. I think for this project i could use an AXI BRAM to do that. How would i go about it? Any resources i could look up? Thanks in advance!!