noraj

Hello, I am working on running L4Linux on Zybo Z7 7020. I am using u-boot 2018 for a sd card boot. The contents on my sd card are BOOT.bin bootstrap.uimage zybo_z7.dtb This is the serial dump, I checked the #define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL , my baud rate is 115200. Xilinx First Stage Boot Loader Release 2021.2 Aug 30 2023-16:24:53 Devcfg driver initialized Silicon Version 3.1 Boot mode is SD SD: rc= 0 SD Init Done Flash Base Address: 0xE0100000 Reboot status register: 0x60600000 Multiboot Register: 0x0000C000 Image Start Address: 0x00000000 Partition Header Offset:0x00000C80 Partition Count: 3 Partition Number: 1 Header Dump Image Word Len: 0x000F6EC0 Data Word Len: 0x000F6EC0 Partition Word Len:0x000F6EC0 Load Addr: 0x00000000 Exec Addr: 0x00000000 Partition Start: 0x000075D0 Partition Attr: 0x00000020 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xFFD13B7E Bitstream In FsblHookBeforeBitstreamDload function PCAP:StatusReg = 0x40000A30 PCAP:device ready PCAP:Clear done Level Shifter Value = 0xA Devcfg Status register = 0x40000A30 PCAP:Fabric is Initialized done PCAP register dump: PCAP CTRL 0xF8007000: 0x4C00E07F PCAP LOCK 0xF8007004: 0x0000001A PCAP CONFIG 0xF8007008: 0x00000508 PCAP ISR 0xF800700C: 0x0802000B PCAP IMR 0xF8007010: 0xFFFFFFFF PCAP STATUS 0xF8007014: 0x00000A30 PCAP DMA SRC ADDR 0xF8007018: 0x00100001 PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0 PCAP DMA DEST LEN 0xF8007024: 0x000F6EC0 PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF PCAP MBOOT 0xF800702C: 0x0000C000 PCAP SW ID 0xF8007030: 0x00000000 PCAP UNLOCK 0xF8007034: 0x757BDF0D PCAP MCTRL 0xF8007080: 0x30800100 DMA Done ! FPGA Done ! In FsblHookAfterBitstreamDload function Partition Number: 2 Header Dump Image Word Len: 0x0002115E Data Word Len: 0x0002115E Partition Word Len:0x0002115E Load Addr: 0x04000000 Exec Addr: 0x04000000 Partition Start: 0x000FE490 Partition Attr: 0x00000010 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xF7E9E4E4 Application Handoff Address: 0x04000000 In FsblHookBeforeHandoff function SUCCESSFUL_HANDOFF FSBL Status = 0x1 U-Boot 2018.09-00427-g4024652143-dirty (Sep 01 2023 - 17:07:44 +0200) CPU: Zynq 7z020 Silicon: v3.1 Model: Digilent Zybo Z7 board I2C: ready DRAM: ECC disabled 1 GiB MMC: sdhci@e0100000: 0 Loading Environment from SPI Flash... SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB OK In: serial@e0001000 Out: serial@e0001000 Err: serial@e0001000 Net: ZYNQ GEM: e000b000, phyaddr 0, interface rgmii-id Warning: ethernet@e000b000 (eth0) using random MAC address - d2:c0:0a:7b:ee:5a eth0: ethernet@e000b000 Checking if uenvcmd is set ... Hit any key to stop autoboot: 0 ** Unable to read file uImage ** 11258 bytes read in 13 ms (845.7 KiB/s) ## Booting kernel from Legacy Image at 03000000 ... Image Name: L4 Image #20 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1914800 Bytes = 1.8 MiB Load Address: 01000000 Entry Point: 01000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 02a00000 Booting using the fdt blob at 0x2a00000 Loading Kernel Image ... OK Loading Device TúHqÈâámjâÃÂãÀÃÂâÐÀààÁòðýHØÀÚøÈàÀÂÂÁò`ÐÉ`èaêàÙðÁÛéXðÐéãÃàøÙùÃêÉBúéaøiÈÊÙˤÊmøaúiÈÈÊÙˤÊmøaúiÈÊÙËpøøÈú¤ÊméaøiÈÊÙˤÊmøaúiÈÊÙËpøøÈú¤ÊmÊÙËapøøÈú¤ÊméaøiÈÊÙˤÊmøaúiÈÊÙËpøøÈú¤ÊméaøiÈÊÙˤÊmøaÚiÈÈÊÙˤÊmøaúiÈÊÙËpøøÈú¤ÊméaøiÈÊÙˤÊmøaúiÈÊÙËpøøÈú¤ÊmÊÙËapøøÈú¤ÊméaøiÈÊ I also checked the zybo_z7.dts had the clock freq to 50MHz slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <0x01>; #size-cells = <0x01>; compatible = "xlnx,zynq-slcr\0syscon\0simple-mfd"; reg = <0xf8000000 0x1000>; ranges; phandle = <0x09>; clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <0x01>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0x0f>; clock-output-names = "armpll\0ddrpll\0iopll\0cpu_6or4x\0cpu_3or2x\0cpu_2x\0cpu_1x\0ddr2x\0ddr3x\0dci\0lqspi\0smc\0pcap\0gem0\0gem1\0fclk0\0fclk1\0fclk2\0fclk3\0can0\0can1\0sdio0\0sdio1\0uart0\0uart1\0spi0\0spi1\0dma\0usb0_aper\0usb1_aper\0gem0_aper\0gem1_aper\0sdio0_aper\0sdio1_aper\0spi0_aper\0spi1_aper\0can0_aper\0can1_aper\0i2c0_aper\0i2c1_aper\0uart0_aper\0uart1_aper\0gpio_aper\0lqspi_aper\0smc_aper\0swdt\0dbg_trc\0dbg_apb"; reg = <0x100 0x100>; ps-clk-frequency = <50000000>; phandle = <0x01>; }; rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <0x01>; syscon = <0x09>; }; Please kindly help me as I have tried all the tweaks but I just get gibberish.