Hi everyone, I´m new to FPGA development and I´ve been trying to implement an complex number divider following the formula
to do that I´ve done multiple attempts as , using 2 sequential dividers and 2 sequential multipliers, a combinational divider and the two sequential dividers, and for last one sequential divider and a combinational multiplier.
In all the cases referred before I end up using about 1300 LUTs, when I was aiming to 900/1000, where theoretically i would only use about 800 with the modules (180 for seq multiplier, 207 for seq divider , 400 for comb multiplier).
I´ll leave the implementation where i use one combinational multiplier and two sequential dividers so if any of you see something that might be leading to the problems im facing , ill be very thankful.
module cpxdiv_4(
input clock,
input reset,
input run,
input [15:0] ReA,
input [15:0] ImA,
input [15:0] ReB,
input [15:0] ImB,
output[31:0] ReY,
output[31:0] ImY,
output busy
);
wire busy2;
reg [31:0] temp_reg1, temp_reg2, temp_reg3;
reg [31:0] sum;
reg run2;
reg [31:0] dividend_re, dividend_im;
reg [15:0] divisor;
//counter_var
reg state;
reg [7:0] counter;
parameter IDLE = 0,
RUN = 1;
psddivide_top
psddivide_top_1
(
.clock(clock),
.reset(reset),
.run(run2),
.busy(busy1),
.dividend(dividend_re),
.divisor(divisor),
.quotient(ReY),
.rest()
);
psddivide_top
psddivide_top_2
(
.clock(clock),
.reset(reset),
.run(run2),
.busy(busy2),
.dividend(dividend_im),
.divisor(divisor),
.quotient(ImY),
.rest()
);
// Clock cycle counter implementation
always @(posedge clock)
begin
if ( reset ) // Synchronous reset, active high
begin
state <= IDLE;
counter <= 8'd0;
end
else
begin
case ( state )
IDLE: if ( run )
begin
state <= RUN;
counter <= 8'd1; // this is the start value show in the timing diagram
end
RUN: if ( counter == 8'd46 ) // last clock cycle
begin
counter <= 8'd0;
state <= IDLE;
end
else
begin
counter<=counter+1;
end
endcase
end
end
always @(posedge clock)
begin
case(counter)
9: run2 <= 1;
11: run2 <= 0;
endcase
end
always @*
begin
case(counter)
1: temp_reg1<= fxpmult(ReA,ReB);
2: temp_reg2<= fxpmult(ImA,ImB);
3:begin
dividend_re <= temp_reg1 + temp_reg2;
temp_reg3<=fxpmult(ReB,ReB);
end
4:temp_reg1<= fxpmult(ImB,ImB);
5:begin
sum <= temp_reg1 + temp_reg3;
temp_reg2<=fxpmult(ReB,ImA);
end
6: begin
temp_reg3<=fxpmult(-ReA,ImB);
divisor<=sum[31:16];
end
7:dividend_im<=temp_reg2+temp_reg3;
endcase
end
assign busy = ( counter >= 8'd1 && counter <= 8'd50 );
function [31:0] fxpmult (
input[15:0] A,
input[15:0] B
);
reg [15:0] absA;
reg [15:0] absB;
reg [31:0] P;
reg sP;
begin
sP = A[15] ^ B[15];
absA = A[15] ? -A : A;
absB = B[15] ? -B : B;
P = absA * absB;
fxpmult = sP ? -P : P;
end
endfunction
endmodule
