Paul_at_PTest

I had this same problem, I am using Vivado v2023.1 (64-bit) and Vitis IDE v2023.1.0 (64-bit). My Vivado block diagram worked fine as long as I did not instantiate my custom AXI4Lite IP. When I instantiated my custom IP, Vivado continued to work fine, producing the bitstream. I would then export it to Vitis, Update Hardware Specification, and then try to build and I would get the makefile errors, surrounding the makefile for my custom IP. I then did BOTH of the edits recommended above by Antonio, and this worked for me.