Chris RF

Just on the IDELAY, it took me a while to figure out, but they can actually be inserted between fabric to fabric connections. Vivado seems to do a bad job with them though so I've had to lock their posititions to avoid routing failures. I'm not using them to simulate differential matching as you suggest, just to control delays from one pair to the next. It looks like Digilent won't supply trace length information for their boards and also no gerbers so my plan to compensate through extra trace lengths on my board will only be possible if I measure trace delays which seems like a bad idea. I'll consider a single ended to LVDS converter because that would certainly make the problem go away. Initially I'm worried about the jittter performance of that route. I have used the Z7 for another project so that's what I feel comfortable with. The CMODA7-35T looks like it might work, but I'll need another Arm dev board with ethernet and a command connection to the CMOD for that to work for me. I'll look at the Mimas-A7 as well. Thanks for your thoughts! I appreciate it.

Hi Zygot, If I can get the Z7's trace lengths then I will compensate for differences between P and N outputs of each pair via traces on the PCB that plugs onto the Z7. I don't care about time differences from pair to pair, as they will be compensated in the FPGA. Each pair will be turned into a single ended 50 ohm signal via a transformer, so I need the P and N to be well matched for clean transitions. I need 16 balanced outputs (so 32 balanced output pins) and 2 balanced inputs (so four more balanced input pins). I notice the series resistors put into some of the Z7 traces so they would need to be linked out which is admittedly painful. One alternative is to lay out my own board similar to the Z7, but that is a big investment for what is likely to be around 5 that I need for now.

I'm planning to use nearly all of the Z7's pins to provide balanced outputs in a timing critical application. Is there a report available for the trace lengths, delays and impedances for each FPGA trace to each associated header pin?