sean789

Hello, I am using the CMOD A7 -35T in Vivado 2022.1 and haven't been able to find the timing constraints for the cellular ram (SRAM) on the board. I have the board files and physical pin location and drive type constraints from github ( https://github.com/Digilent/Cmod-A7-35T-GPIO/blob/master/src/constraints/CmodA7_Master.xdc) , but they don't seem to have the timing constraints, only a single clock constraint. I have opened the OOB demo from Github and run through synthesis and implementation but the post implementation timing report shows that the IO to the SRAM and and QSPI Flash are unconstrained. Is constraining these ports left to the user?