Hi @zoodle
You are correct, that looks to be a mistake in the guide. If you continue through the guide to the point where an HDL wrapper is created and open the HDL wrapper, you will be able to see the top-level port names in the port list, these top-level ports are the names that the constraints must match. The port will appear as either gpio_tri_io, gpio_tri_i, or gpio_tri_o, depending on whether the GPIO IP is set to tristate, all input, or all output. The three ports you see on the IP end up getting automatically connected to a tristate buffer in the final design.
Thanks
Arthur
