DougFPGA

Note: I haven't personally done this (yet) so others with more experience can correct me. I'd look into building an AXI interface directly to the block RAM. Xilinx seems to provide one as an IP block in PG078, "LogiCORE IP AXI BRAM Controller v4.0". Then you should be able to read the block RAM directly from the PS with the appropriate memory addresses. Cheers, Doug