CBI

Hi @Niță Eduard, Yes that was it!! Thanks a ton!! Should have paid more attention to the video resolutions!! For folks who are starting out on this, I have created a step by step tutorial. https://gitlab.ssec.wisc.edu/cbabu/pcam_edge_detection Regards, Charls

@JColvin @Niță EduardThanks for the update!! I tried a couple more things: 1. Edited the edge_detection.c file to remove edge detection, now it just converts the AXIvideo to xfMat and back : #include "edge_detection.h" void edge_detect(stream_t& stream_in, stream_t& stream_out1)//, stream_t& stream_out2) { #pragma HLS INTERFACE ap_ctrl_none port=return #pragma HLS INTERFACE axis port=stream_in #pragma HLS INTERFACE axis port=stream_out1 //#pragma HLS INTERFACE axis port=stream_out2 //xf::cv::Mat-type local variables for intermediate results xf::cv::Mat<XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img0(MAX_HEIGHT, MAX_WIDTH); //xf::cv::Mat<XF_8UC1, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img1(MAX_HEIGHT, MAX_WIDTH); //xf::cv::Mat<XF_8UC1, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img2x(MAX_HEIGHT, MAX_WIDTH); //xf::cv::Mat<XF_8UC1, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img2y(MAX_HEIGHT, MAX_WIDTH); //xf::cv::Mat<XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img3x(MAX_HEIGHT, MAX_WIDTH); //xf::cv::Mat<XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> img3y(MAX_HEIGHT, MAX_WIDTH); #pragma HLS DATAFLOW //Interpret AXI-Stream interface and pull the frame from it xf::cv::AXIvideo2xfMat<24, XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1>(stream_in, img0); //Convert to grayscale //xf::cv::rgb2gray<XF_8UC3, XF_8UC1, MAX_HEIGHT, MAX_WIDTH>(img0, img1); //Run the Sobel operator on the x-axis with a 3x3 kernel //xf::cv::Sobel<XF_BORDER_CONSTANT,XF_FILTER_3X3,XF_8UC1,XF_8UC1,MAX_HEIGHT,MAX_WIDTH>(img1, img2x, img2y); //Convert back to RGB format for display purposes //xf::cv::gray2rgb<XF_8UC1, XF_8UC3, MAX_HEIGHT, MAX_WIDTH>(img2x, img3x); //xf::cv::gray2rgb<XF_8UC1, XF_8UC3, MAX_HEIGHT, MAX_WIDTH>(img2y, img3y); //Pack the frame back into AXI-Stream interface //xf::cv::xfMat2AXIvideo<24, XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1>(img3x, stream_out1); xf::cv::xfMat2AXIvideo<24, XF_8UC3, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1>(img0, stream_out1); } 2. I compiled this, the timing violation still persist (which is expected as the violation is in a datapath that does the conversion). 3. After importing the IP in Vivado, I noticed the connection wizard was prompting for auto connection. Upon clicking, it now instantiates a new block called Processor System Reset. The clk_out2 which is connected to my IP goes to this, and a reset is generated which is routed to the HLS IP. (Earlier I was connecting the peripheral_aresetn from the other processor system reset which was generated on clk_out1.) The output is still the same though(blank screen). Now, I am pretty sure the issue is something trivial involving the interface. 4. Next I tried a run with just stream_out1 = stream_in; though I'm not sure if this is a legal assignment in HLS. (Same black screen) Thanks!! Appreciate your help!!

Hi @Niță Eduard@filipj, I see you guys have got the Embedded Vision Workshop working on Vivado 2020.1!! I have been trying to get it to work on my setup for some time now. These are the things that I have tried so far, but all i get is a blank screen when I pass the AXI stream through an HLS compiled block. Steps: 1. I started by getting the raw video out by following the steps from: https://digilent.com/reference/learn/programmable-logic/tutorials/zybo-z7-pcam-5c-demo/start So the basic video pipeline is working and the Zybo setup is good. My problems start with Vitis HLS: 2. To create the edge_detect IP, I copied the necessary files from @Niță Eduardpost from Dec 10 2020. I kept the period to 6.67 (Based on the Workshop pdf.) On compilation, I get the following timing violation. 3. I still went ahead and exported it as Vivado IP(zip file). 4. I imported the hw.xpr of the corresponding Digilent SW library and opened the block diagram in Vivado. Here I made the following connection changes: i) M_AXIS_MM2S -> stream_in ; stream_out1 -> video_in ii) ap_clk -> clk_out2 iii) ap_rst -> peripheral_aresetn[0:0] 5. Exported the design XSA. 6. Imported Hardware platform into Vitis IDE, and launched on hardware. Result: I only get a blank screen on my monitor. If I bypass the HLS block in my block diagram(from step 4) and repeat the whole process, I get a good feed. Troubleshooting done so far: 1. Tried with axiconv as stated above, same result. 2. I tried if I could pass the feed through some already existing IP like a switch or broadcaster but no luck there either. 3. Tried changing the clock period to 10, nothing(The timing violation goes away though) 4. Initially tried with the 2020.2 suite, now on 2022.1. 5. Finally, just for the kicks, I tried booting the zybo with the pre-compiled .bin found on the tutorial, and it works just fine!! Edge detection and all!! Question : Do i need to set up the OpenCV flow, if I am not planning on running simulations? My understanding is that for running directly on the hardware, the vision libraries do not need OpenCV installed. It would be really great, if there was an updated tutorial as the existing ones use Vivado SDK. That said, I plan to prepare a detailed one and share it if I can get this working!! Thanks!!!