manjagu

Hi All, I'm trying to replicate what was done above by the OP with my Arty A7-35 on Vivado 2022.2.1. When I use the default mig.prj ver 1.1, I get stuck without the chip option MT41K128M16JT-125. The default is the -15E, which has some speed limitations, and the MIG wizard won't let me proceed to take the clock speed up. I double checked my board and it is populated with the -125. I've tried a few work-arounds, including manually editing the mig.prj file, and I just get myself into various other sticky places. I'm trying to use the new Xilinx "recommended" clocking scheme rather than putting the PLL before the MIG. Any recommendations?