R2COM

So do you use GHDL with Xilinx libraries as well? Do you use Modelsim from Quartus to compile libs from Xilinx and other vendors other than Intel? is it doable? Or do you use GHDL for everything?

well that is the reason why modelsim used in production environments, because it IS important to customers, X conditions due to some contention etc. caught in sim (of course large portion of it is caught in synthesis), however; ill formed testbench also can lead to it. by the way, I didn't want to limit discussion only to Verilator, although it was main topic, however; I did more research and found that icarus on the other hand does not support sv2017. And I'm sure it also will have issues compiling standard primitives (again, main question was about standard primitives libraries, not encrypted cores) also, I found something like Surelog--->UHDM--->Simulator (Verilator, etc) constructs online. If anyone ever had to do anything with it, please comment. So the above chain it means can allow taking SV2017, and effectively compile it to something what Verilator AND Icarus can take as input and simulate? although its quite unclear to me how would I debug behavioral declared signals... (would be as hard as debugging base logic using back annotated sims where everything is mixed into cells) So it seems there is no place for open source fpga development in professional production environment (again most of such environments DO have necessary $$$ to purchase soft) its just I was (for fun) researching, with what tools I can do same what I do during my dayjob using just free tools, seems the answer is - none.

I've been seeing similar topics here long ago, but as of today wanted to figure out few things regarding Verilator. 1) Can verilator compile Xilinx simulation libraries? 2) I have seen this pointed out few times online but noone really addressed it - Does simulation in Verilator handle X conditions on signal or it ignores it? Because I heard it ignores it (meaning signal can be 1 or 0); If yes, it would be a huge no go for me, since for verification I need to see if design wrongfully asserts X on something. 3) Can one do back annotated development/sims with verilator? In my day job, I do this a lot with big3 sims and synthesis/par tools - i.e. when design is synthesized and routed I feed back top structured HDL file as well as timing files for back annotated sim. Is there any open source tool which can do SystemVerilog2017 and at the same time support this?