AndreaGonzalez

Hello, I would like to use the DD logic analyzer to capture data from an 8-bit parallel bus. I also want to connect an external clock, synchronous to the data bus, to synchronize this data with the internal sampling clock of the DD. I have read about the sync mode to do this, but I still don't completely understand how it works. Since the DD does not support sampling at the external clock, how can I guarantee that there will not be wrong samples on transition edges since my bus will be asynchronous to the DD internal sampling clock? If the sync mode is set to a different sampling rate does the sync mode only captures data when it sees the external clock transitions? Also, does the synch mode only captures data on both edges of the external clock? I read in other questions that the triggers are not available in this mode and it has to be set to "edge". Will this cause repeated samples in the captured data? Just for reference my external clock will be 7.5MHz and I want to capture data at 15MHz min. Thank you,