hlittle

@JColvin, thanks. @D@n, With the *micro* sd pmod, pin 10 is potentially connected to the enable line of the power regulator. The reference does list pin 10 as NC, but the schematic suggests that it could be used to power cycle the sd card, if that part of the circuit is present :-) The Nexys A7 board has the ability to power cycle the on-board micro sd card. I am just wondering if that feature exists with the pmod too. My hope was to use the power cycle as an fail safe reset in case the sd card got into an uncooperative state. Without the ability the power cycle the sd card, what's the next best way to reset an sd card (in spi mode)? Is toggling the chip select line and sending cmd0 the best we can do?

Hi, Can anyone confirm or deny that the micro sd pmod allows the fpga to power cycle the sdcard? The schematic seems to imply that the functionality is supported, but it says the parts are not loaded. However, in the pictures of the pmod, it looks like the parts are present (everything seems to be there, except for R6 and R15, zero ohm resistors). So there is an inconsistency there. Do the pmods come as pictured? And if so, is it correct that I would need to just add R6 to enable the powercycling capability? Thanks

Thanks for the info. I have read about the clocking resources, and I have written an app that can enumerate all the configurations to achieve a given frequency. The question is given two configurations, which one is better (where I define better as lower jitter)? For example, is a higher VCO frequency better for output jitter? Are integer divisors better than fractional divisors? It is not clear to me from the docs. The application is digital audio. When transmitting digital audio, it is desirable to minimize jitter on the signal. My thinking is that if I have two possible configurations to achieve a desired output frequency, then I might as well choose the configuration that provides the lower jitter. In the clocking wizard, changing the jitter optimization between "minimize output jitter" and "balanced" options, causes the mmcm configuration to change, and even to change the output clock frequency sometimes. So, as an example, suppose I need 98.5MHz. I found three configurations that can generate 98.5MHz from a 100MHz clock (in the Nexys A7): Found 98.5 = 100.0 / 4 * 24.625 / 6.25 (615.625) [309ps] Found 98.5 = 100.0 / 5 * 49.25 / 10.0 (985.0) [246ps] Found 98.5 = 100.0 / 8 * 49.25 / 6.25 (615.625) [514ps] The VCO frequency is in brackets, and the reported jitter is in square brackets. To get the jitter values, I entered each configuration into the clocking wizard manually. So, given the different configurations have different jitters. Why does the second configuration have lower jitter? How is the jitter calculated? The clocking wizard, when set to "balanced" jitter optimization, yields the second configuration. When set to "minimize output jitter", it wants to give me 98.52941MHz: 98.52941 = 100.0 / 1 * 8.375 / 8.5 (837.6) [140ps] The reported jitter is lower at 140s. Is it lower because the initial divisor (ie 1) is lower than 4, 5, or 8 above? So maybe my question really boils down to how is the clocking wizard calculating the jitter value. And I agree that maybe a question for Xilinx. In the meantime I was hoping someone might have a rule of thumb about which configuration would minimize the jitter.

Hi, Can someone explain in simple terms how the Clocking Wizard chooses the suggested configuration to produce a given frequency out of the many possibilities? I understand the calculation and constraints, but my question is really, given two valid configurations that will produce the desired output frequency, what are the rules of thumb to choose one configuration over another? How is the output jitter calculated? How can we minimize output jitter for a requested output frequency? Thanks