Tommy1404

Hi all, i own a Arty-A7 Board and want to run a Microblaze µC completely via the XIP-Function from my Configuration QSPI-Flash or better also partially from BRAM. Is this generally possible without much effort? I already found: https://support.xilinx.com/s/article/46503?language=en_US https://docs.xilinx.com/v/u/en-US/xapp1176-xip-axi-quad-spi-ipi But i think i need more detailed information how to realize it. The Xilinx Application note lets some questions unanswered. When i tick "XIP-Mode" in the QSPI-Flash IP Core a second AXI-Interface on the SPI IP Core is generated. When i connect it to the Microblaze AXI4-Lite Bus via the Interconnect IP-Core, can i address the QSPI-Flash like ordinary ROM-Memory at the specified address in the address editor? When i export the Hardware the QSPI Flash addressroom does not occur in the Hardware memory map in Vitis. Is it intended to just add the memory region manually in the linker script? Regards Thomas