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DiegoGM

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Posts posted by DiegoGM

  1. Thanks so much, @zygot

    I'll certainly check this HDL design flow example you shared with me. I noticed that I wasn't clear enough with my question. What I mean is, is it possible to use an ILA with the zybo-7020 board because it does not have a JTAG-HS3 port, only a micro USB port (UART, JTAG). I have a working design in the PL to capture that includes an ILA. I generated a bitstream and attempted to program the FPGA from Hardware Manager using the bitstream file (.bit) and the debug probes file (.ltx); however, the Hardware Manager states that there are no debug cores despite the fact that there is a debug probes file that I select when attempting to program the FPGA. Please see the picture attached for clarification. So I thought that I may need to use JTAG-HS3 programming cable / debugger in order to configure the ILA with the .ltx file. Is this assumption correct?

     

    I look forward to hearing from you. 

     

    image.thumb.png.9d9c42bc83b2c7178b09133edd97ad20.png

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