Udayan Mallik

@JColvin dpmutilFSetFanConfig(fanid, setEnable, enable, setSpeed, speed, setProbe, probe); What values should be used for the command. Since there is no fanid, setenable, enable, setspeed variables in the three Structs - what values do they accept? And what is their range? My FPGA is becoming very warm and might go up in smoke without a Fan.

@artvvb @zygot I have been trying to work with the routines that I downloaded from https://github.com/Digilent/Eclypse-Z7-SW/tree/dpmutil Does the full code compile in Vitis. If not, what values should be used in the command that controls the Fan's settings. dpmutilFSetFanConfig(fanid, setEnable, enable, setSpeed, speed, setProbe, probe);

@TommyK @artvvb Is the latest version in the Master branch?

@artvvb I have implemented a 1Gbps Ethernet link between my Laptop and the Eclypse Z7 card. I have executed both the tcp_perf_server and tcp_perf_client routines on the link. I have attached the output of the iperf command in each case - FPGA acting as server and client. All the performance tests produce numbers much less than the Max rating of the link. The links is rated at 1Gbps on each side (Laptop and FPGA) (see images Connection_Speed.png and Ethernet_Link _as_seen....png). 1. If I connect a high data rate system to this link - camera or controller - what is the best data rate possible on this link. 2. Is the link 1Gbps in each direction? 3. Is there anything preventing it from acting as both client and server? Both Uplinking and Downlinking data? If I install an OS the ethernet link will be able to both receive data and send data. Is that merely a link that is operating as both server and client? 4. Is IPV6 faster than IPV4? What is the difference between the two protocols?

@artvvbI have solved this problem. I disabled the IPV6 option and used the IPV4 option instead

@artvvbTo test the tcp_perf_server the runtime messages suggest running the following line of code on my (Laptop) system iperf -V -c FE80::20a:35ff:FE00:102%<interface> -i 5 -t 300 -w 2M What is %<interface>?

@artvvb After much experimentation my lwip_echo_server routine is now operational. I can ping an Eclypse Z7 card. Since I use Vitis 2021.2 a large part of online help tends to be useless. I proceeded as follows. 1. To confirm that the Realtek PHY chipset can communicate with a Zynq FPGA I used the document found here https://media.digikey.com/pdf/Data Sheets/Digilent PDFs/Eclypse_Z7_HRM_Web.pdf 2. To use lwip resources I altered the Board Support Package in Vitis. A. In the Platform project - Double click the Platform.spr file. B. Click the ps7_cortex_a9->Zynq fsbl->Board Support Package Tab in the drop down menu. C. Click on the "Modify BSP Settings ..." tab near the top of the page. i. In the Overview tab - Select lwip211 libraries. ii. Then click the Standalone tab. Set the use_axieth_on_zynq to 0 (since the ZYNQ GEM will be used). D. Click the ps7_cortex_a9->Standalone on ps7_cortex_a9_0 E. Click on the "Modify BSP Settings ..." tab near the top of the page. i. In the Overview tab - Select lwip211 libraries. ii. Then click the Standalone tab. Set the use_axieth_on_zynq to 0 (since the ZYNQ GEM will be used). F. Create a new Application program with the lwip_server_echo option (instead of Hello World) and voila! You have ethernet connection. You can ping IP address 192.168.1.10.

The Eclypse Z7 card is designed to use the lwIP routines to communicate on the Ethernet bus. https://media.digikey.com/pdf/Data Sheets/Digilent PDFs/Eclypse_Z7_HRM_Web.pdf "For getting started using the ethernet port in a bare-metal application, Xilinx provides a lwip TCP/IP stack that can be automatically generated in Xilinx SDK along with an echo server example."

@artvvb I have used the emacps download (From the Board Support Page) to get things going -- I however see runtime errors. I see the three following errors in Run Time: Length Mismatch, Data Mismatch, Error setup PHY loopback. 1. My PHY Layer is implemented with a Realtech RTL8211E-VL chipset. I found that the emacps routines cannot operate that specific PHY layer. I looked at someone's implementation on Youtube that claims to have solved the problem. and she merely deleted the "exit on error" lines of code from her software. I see that when I do the same, I see some form of output on the receiver PC (Wireshark). I am not sure whether what I am looking at is correct. 2. How do I find the IP address of the device. 3. I am also working with LWIP. Will it be able to establish an Ethernet connection given that it also has to communicate using the RealTech PHY?

@artvvb I am working on enabling the Ethernet port in Eclypse Z7. In the block diagram I see that ENET 0 is checked. When I double click ENET 0 I am taken to a page where I select MDIO (MIO 52 ... 53). However, no PINS are created as result. Without pins I cannot create a constraints file. In addition - after making the selections and closing the dialog box, I reopen the dialog box to check whether the selections are still in place. They are NOT. Is this an error? How do I enable the Ethernet link in Eclypse Z7.

@artvvbI am using an Eclypse Z7. I am required to use a Camera with it that is GeniCam and GigE Vision compatible. Is the Eclypse Z7 GeniCam and GigE Vision compatible - in Linux mode? Bare Metal mode? My preference is to use the system in Bare metal mode.

My project requires the use of a GigE Camera with an Eclypse Z7? Can this be done - specially in Bare Metal Mode? All cameras come with an SDK that has to compile on a given platform. Does anyone know of a GigE Camera whose SDK can be compiled using Vitis for the Eclypse Z7?

Can't you use the 1G Ethernet port to communicate with a PC? Is the Ethernet port available in Bare Metal mode? Why do you need a PC? The PS is a fully fledged processor. It can run an OS - therefore it should be able to implement reasonably complex programs for a user. The same chip in the Zedboard can act as a full computer running an OS with a Display. I don't think the full potential of the system is being exploited.

Thank you for your response. I have successfully implemented a sine wave. My equation used to be 3.9*sin(2*3.14*125*(1/100000000)*j*255) - this produces a Sine wave in Matlab (for j = 1:3138) and, if entered in google (try 3.9*sin(2*3.14*125*(1/100000000)*758*255) where j is 758 and can vary between 0:3138) Evidently in an embedded system 1/100000000 = 0 However, since where there is a will there is always a way, changing the said number to 3.9*sin(2*3.14*125*(1/100000000.00)*j*255) does the trick (Converting the 100000000 to a 100000000.00). See image attached.

@JColvinDo you have BOMs for the DAC1411 and ADC1410 cards? In addition, do you have a BOM for Revision E of Zedboard. These files were not available on the websites you provided.

My system defaults to g++. I inserted the m in the libraries list as you suggested. That did not help. The "sin" command still does not produce a sine wave. Is g++ the problem?

@artvvb I am attempting to create a Sine wave using the DAC1411 module. To that end, I have created three functions - 1 that reads a predefined waveform from a file, 1 that attempts to create the waveform on the fly using the math.h library and the sin function, and one that uses an array containing the values of a sine wave inside the function. None of the methods have produced a sine wave. Does Vitis not support complex math and FILE IO functions? Am I not allowed to use arrays? Is the fuinction dacrampdemo predefined/instantiated in a .h file? How do I add my function to that file?

@artvvb Here it is. You are required to modify the "main" routine and the "dacRampDemo" routine as shown below. void dacRampDemo(float offset, float amplitude, float step, uint8_t channel, uint8_t frequencyDivider, uint8_t gain) { ZMODDAC1411 dacZmod(ZMOD_DAC_BASE_ADDR, DMA_DAC_BASE_ADDR, IIC_BASE_ADDR, FLASH_ADDR_DAC, DMA_DAC_IRQ); xil_printf("Not Doing anything\n\r"); uint32_t *buf; float val; uint32_t valBuf_1, valBuf_2; int16_t valRaw; size_t length = (int)(amplitude/step) << 2; int i; if (length > ((1<<14) - 1)) { // limit the length to maximum buffer size (1<<14 - 1) length = ((1<<14) - 1); // adjust step step = amplitude/(length>>2); } buf = dacZmod.allocChannelsBuffer(length); dacZmod.setOutputSampleFrequencyDivider(frequencyDivider); dacZmod.setGain(channel, gain); dacZmod.setGain(channel-1, gain); i = 0; // ramp up for(val = -amplitude; val < amplitude; val += step) { valRaw = dacZmod.getSignedRawFromVolt(val + offset, gain); valBuf_1 = dacZmod.arrangeChannelData(channel, valRaw); valBuf_2 = dacZmod.arrangeChannelData(channel-1, valRaw); buf[i++] = (valBuf_1<<16) | (valBuf_2>>16); } // ramp down for(val = amplitude; val > -amplitude; val -= step) { valRaw = dacZmod.getSignedRawFromVolt(val + offset, gain); valBuf_1 = dacZmod.arrangeChannelData(channel, valRaw); valBuf_2 = dacZmod.arrangeChannelData(channel-1, valRaw); buf[i++] = (valBuf_1<<16) | (valBuf_2>>16); } // send data to DAC and start the instrument dacZmod.setData(buf, length); dacZmod.start(); dacZmod.freeChannelsBuffer(buf, length); } int main() { init_platform(); xil_printf("Hello Eclypse Z7!\n\r"); //xil_printf("Testing ADC ZMOD...\n\r"); // COMMENTED //adcDemo(0, 0, TRANSFER_LEN); // COMMENTED xil_printf("Testing DAC ZMOD...\n\r"); dacRampDemo(-0.05, 3.90, 0.005, 1, 255, 1); cleanup_platform(); return 0; }

@artvvb Thanks for the response. After reading your mail I was able to work out a way to command both channels simultaneously. Do you want the file that allows control of both channels simultaneously?

@JColvin Did you create a 3D Step file for the Eclypse Z7 during this discussion? I, as you know am also looking for the 3D model of the Eclypse Z7. Thanks UM

@artvvb I am using an Eclypse Z7 with a DAC1411 and an ADC1410 to implement a control algorithm. I followed the instruction in https://www.hackster.io/whitney-knitter/hello-zmods-on-the-eclypse-z7-99107d to define the FPGA architecture. However, when I attempt to write to the DACs, I can only access one channel of the DAC at a time. I cannot access both channels simultaneously. The AD9717 datasheet clearly states that the input interface uses a DDR protocol. Is this something the provided hardware can do, or am I required to modify the blocks to produce simultaneous outputs. Udayan Mallik

Thank you @JColvin. Have you had any luck with the Eclypse 3-D Step file? In addition what screw size is used to bolt down the ZMOD cards to the Eclypse Board? Udayan Mallik

I am using a Zedboard and an Eclypse_z7 (with ADC and DAC ZMODS). I am look for 3D-Step files to create a model of the electronics package. Can Digilent make such files available (usually programs like Altium Generate these files). I am also required to model heat dissipation from my cards. Is there a resource available to help this process. Udayan Mallik

I successfully imported your design to 2021.2 I also managed to create my own design using tools made available on github. Thank you.

I bought a Eclypse-Z7 (with the ADC and DAC installed) from Digikey using the link below. What are the respective clock speeds of the DAC and the ADC. https://www.digikey.com/en/products/detail/digilent-inc/471-036/12147357?s=N4IgTCBcDaIIxgBwDYC0AWA7HVAGAzGgHIAiIAugL5A