Udayan Mallik
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Posts posted by Udayan Mallik
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Unfortunately, I do not agree. This is the first time I have seen a distributed git repository. It was a pleasure working with it. I intend to use this method to create storage for complex and distributed developments that cannot be merged - at least not easily. In any case it is something new. Not wanting to learn new things, is the root cause of stagnation.
In so far as Xilinx is concerned, I can only share what I observed. Importing was not difficult. I imported two versions of the code for this project. One - provided by the repository (2019.x) and one I received from someone here, who provided me with a 2020.x version. Both imports went without any incident.
I have been using Vivado for many years - changes come and changes go. We learn to live with them. However, yes, it would be nice to not have to re-learn things every time someone introduces a change. Vivado in my opinion is one of the better software packages on the market.
Similarly, Digilent in my opinion is one of the best companies to work with. They are exceedingly helpful. From what I recall - the git clone command required one or two additional switches. The software took care of the rest all by itself. All they ask is that a user read the README.md files before proceeding. Not much to ask!
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@LHji I had meant the Q&A section to see how Vitis was implemented. There should be only one timing violation. That is the only major warning you should receive from that page. You seem to have help from someone. I hope that resolves your problem.
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Have you tried the Q&A section in "Hello ZMODs on the Eclypse Z7 - Hackster.io" I posted some ideas here when I first started my Eclypse Z7 project.
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@LHji One of the users asked for a version for Vivado 2020.0 here - "Eclypse Z7 libraries & Vivado 2020.2 (or any later version) for a measurement platform - FPGA - Digilent Forum". This is a URL. Try the code attached there from artvvb. You might have to scroll down to find it.
In addition, cloning is not as simple as git clone "Link". The Download for Eclypse Z7 has many dependencies (external). You should read the README.md file before beginning the download. It gives special instructions to help you download what you are looking for. This is the link to Digilent's Github link: "Digilent/Eclypse-Z7 (github.com)" copy and paste what is inside the quotes.
I also do not recall receiving a wrapper from Digilent. I followed instructions listed in "Hello ZMODs on the Eclypse Z7 - Hackster.io" to create a wrapper and hardware.
I found that importing designs from Vivado 2019 to Vivado 2021.2 does not run up against any roadblocks. That bit of the problem does happen to resolve itself thanks to the high-quality Software provided by Xilinx.
Building hardware for Eclypse Z7 requires a considerable amount of effort. No precompiled binaries are available for this project ("Hence my surprise at your assertion to have access to a Digilent provided wrapper.").
On the upside: You can learn a lot of new things about Git. If you are new to Xilinx, you can learn about their software as well.
You should expect to spend a month coming up to speed with new technology if you are new to Git and Xilinx.
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@artvvb I now have a different problem. "Generate Bitstream" does not generate a bit file. I get the attached message - since I do not assign 4 of the pins to any location "An unspecified IO Standard Error" is generated. How do I get around it? Assign random pins to these ports? Do you have a list of pins that cannot harm the operation of the card.
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@artvvb Thank you for your response.
First - I cannot use the board file interface to connect the module to its pins. I do so using the Make External instruction.
Second, I use two AD1 cards. Can I instantiate two AD1 modules in the FPGA and connect the IO of the second to the lower row of the PMOD port?
Udayan Mallik
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@artvvb I am using two AD1 cards to ingest 4 channels of ADC data. As per @JColvin's directions, I instantiated the Pmod_AD1 data handler in my FPGA and connected all 8 ports of that module to 8 corresponding pins in the FPGA.
Does this imply that the Pmod AD1 module is designed to interact with 2 AD1 cards at all times?
Udayan Mallik
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@JColvin Declaring the pins as "External Pins" has resolved the issue. Thank you.
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@artvvbI found this post on the Xilinx Forum that goes into why PIN definitions do not percolate up to the Top level. I do not see any difference between the implementation for ACL2 and AD1 Pmods. Continuing to look.
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@artvvb One of the Critical Warning Messages, generated by the Synthesis engine, and one which @JColvin asked me to ignore - is causing a failure downstream - when I generate a Bitstream for the FPGA. The two attached images show the warning message and the failure message in Vivado.
[Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["/home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/ip/lc402_Analog_PmodAD1_0_0/lc402_Analog_PmodAD1_0_0_board.xdc":4]
The Post titled "Pin assignment Problem - SD Card PMOD." recommends rebuilding the offending module. Can you rebuild the PmodAD1 module for the Eclypse Z7 card?
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@artvvb I receive the following Critical Warning when I synthesize my design. I am not sure what a pmod_bridge _0 is however I read in one of the posts that you can ignore warnings like this from vivado. Can I ignore a critical warning?
[IP_Flow 19-4965] IP pmod_bridge_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:eclypse-z7:part0:1.1'. Please update the project settings to match the packaged IP.
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@artvvb The project archive was 228MB. Do you still want to look at it.
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@artvvb Here it is. Please also note that the PMOD_AD1_0 used to be a PMOD_ACL2_1 in the original design.
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Your best bet is to use the Cores provided by the Manufacturer.
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@artvvb I am receiving the following warning when I change the logic handling Port JB in the Eclypse Z7 from PmodACL2 to PmodAD1. Can someone explain to me what the warnings are referring to? The Create VHDL wrapper command produces these warnings.
Wrote : </home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.srcs/sources_1/bd/lc402_Analog/lc402_Analog.bd>
Wrote : </home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.srcs/sources_1/bd/lc402_Analog/ui/bd_22473550.ui>
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_bid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_rid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon/M00_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon/M00_AXI_wid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon/M00_AXI_arid'(1) - Only lower order bits will be connected.
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/synth/lc402_Analog.vhd
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_bid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_rid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon/M00_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon/M00_AXI_wid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon/M00_AXI_arid'(1) - Only lower order bits will be connected.
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/sim/lc402_Analog.vhd
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/hdl/lc402_Analog_wrapper.vhd
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@artvvb I generated a bit stream for the Eclypse Z7 with two PMODACL2 blocks controlling IO through JA and JB. I now want to use a PMODAD1 device to interact with an analog source. Can I use the PMODACL2 interface to acquire data form the PMODAD1 device?
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@JColvin dpmutilFSetFanConfig(fanid, setEnable, enable, setSpeed, speed, setProbe, probe); What values should be used for the command. Since there is no fanid, setenable, enable, setspeed variables in the three Structs - what values do they accept? And what is their range? My FPGA is becoming very warm and might go up in smoke without a Fan.
Zmod DAC1411 maximum sample update rate problem
in Add-on Boards
Posted
@zygot I do hope you found what you were looking for. Yes, a blind git clone "LINK" is better than understanding whatever the README.md file says on the Eclypse Z7 page. It is not pleasant. However, I see it as a way to keep up with new Technology and new ways of doing things. Have a nice day.