Jump to content

viren

Newcomers
  • Posts

    1
  • Joined

  • Last visited

Everything posted by viren

  1. Hello! I am facing a strange issue, for which I seek your support to rectify it. On a ArtyA7-100T, I have a Microblaze based design with DDR, QSPI & UART + custom peripherals. The bitfile is exported to Vitis and I am creating two application projects: one for SREC SPI bootloader & other for my application which i want to run from DDR. Currently, the scenario is following: I have programmed bitfile(with BL configured) in flash at 0 offset occupying upto 0x3B0000. And I have flashed my Application program in flash at 0x3B0000 offset. Now, if i press PROG button, things boot nicely, and my Application start running. But, if I press RESET button, then everything goes silent, i can still see fpga prog light being lit, but my application no longer runs or invokes. Can someone please help me in understanding is this an expected behavior or have I missed something crucial in creating Block diagram or in generating elf ? My doubt is on reset vector. Currently in linker script, its at 0x0 . Thanks & Regards, Viren Ramchandani
×
×
  • Create New...