Well, I worked out just now. I just set the sys_clk to 100MHz, and connect the pmod interface ja(3 to 4) to scl, sda. I am using ArtyA7-100T, I am not sure why picking up 100 MHz as the internal clock frequency of board is 450MHz. I get the 14 bit data from hum and tem registers. The VHDL source file is from digikey as is the last post.