johnsomu

That's excellent! Thanks Atilla

I have a feature suggestion based upon my initial experience with Digital Discovery. I think it would be very useful for the sync mode to be able to use more than one clock source to trigger the capture - this is a feature that I use on my HP 1640G logic analyzer. It can take 3 clocks as J, K and L inputs with selectable rise, fall or either edge triggers ORed together. This is required for capturing parallel bus data where there are separate READ and WRITE lines, such as the PATA bus. To get around this I have set up an external XOR gate with the READ and WRITE lines feeding the inputs and the gate output being sent to the Digital Discovery input designated as the sync source. I think it would be much better to be able to designate at least two inputs as sync clocks so both the READ and WRITE operations can be captured without using external hardware. >>Since I've written this I've found that in my case I need to add a delay to the READ and WRITE signals captured on the DD so that I can tell what they *were* just prior to them being unasserted. This is because the bus data is written or read after the signals are unasserted, and once the XOR gate clocks the capture on the tail end of the READ or WRITE pulse the lines no longer show what the operation was. The data is correct though.