shihwen

Hi @elodg, Really thanks, I don't notice this warning. BR, Eddie

Yes, the mmcm is placed at Bank14, not Bank34. But it seems to relate to bank voltage. For attached file, please run the run_syn_fpga in eddie_script. Thanks for your help.

Hi elodg, I attached my project file and I will check the log later. Please guide me, thanks you. BR, Eddie clock1.rar

Hi elodg, Thanks for your reply. I'm sure I have assigned the input and output ports in my xdc file. set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports pllfout] create_clock -period 10.0 -name clk_100m -waveform {0.0 5.0} -add [get_ports pllfout] set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { clk_out1 }]; set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { clk_out2 }]; set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { clk_out3 }]; set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { clk_out4 }]; set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { locked }]; set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { set_vadj_en }]; set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { ext_reset_n }]; set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] But I don't know why the vivado always want to arrange the pllfout port to LVCMOS18? Refer to my attahed photos, you could see the clk_out1, clk_out2, clk_out3, clk_out4 and locked are assigned to BANK34 with bank voltage is 3.3V. The package pin R4 is also at Bank 34, but I don't know why the pllfout could not use it? Instead, it is assigned to U20 of Bank14 with bank voltage 1.8V. But I have declared the CFGBVS is VCCO. I really don't understand it. please help. BR, Eddie

The error message reported from vivado is ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 10 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pllfout. ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 10 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pllfout. INFO: [Vivado 12-3199] DRC finished with 2 Errors

Dear Sirs, I am using the wizard clock and try to generate a bit file, but I suffer 2 drc errors (note1). please help me. My xilinx board is Nexys video with XC7A200T-1SBG484C 1.The verilog code is as photo1 2. The schematic is as photo2 3. The constrain for clock is set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {pllfout}] create_clock -add -name sys_clk_pin -period 10.0 -waveform {0.0 5.0} [get_ports pllfout] 4. The package pin R4 at bank 34 which is HP I/O of XC7A200T-1SBG484C. According to the schematic, the SYSCLK comes from the oscillator DSC1101CE1 and connect to R4 of BANK 34. (Photo3) I looks like there is a problem to place the clock source port (pllfout), I try the 2 constrains as below in my xdc set_property SEVERITY {Warning} [get_drc_checks NSTD-1] set_property SEVERITY {Warning} [get_drc_checks UCIO-1] But I found the vivado just use another package Pin U20 for pllfout, but the clock source is already assigned at Package pin R4 on PCB board, I think it should not a correct solution. May I learn how to fix this problem? Thank you in advance BR, Shihwen note1: ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 10 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pllfout. ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 10 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: pllfout. INFO: [Vivado 12-3199] DRC finished with 2 Errors