Balaji G K

Hi, We have a internal controller trying connect with Digilent JTAG HS2 debugger and we see Tap error in our metaware during connection. When the TCK is set at -prog dig speed = 1MHz , we get tap error in metaware , but when the TCK set at 5MHz or 10MHz we dont see the error in connection. We have waveforms where in at 1MHz TCK, in TMS waveform we see bus is left idle without any from controller or debugger and it raises sluggishly with internal pullup inside our controller , which seems to be creating some electrical compatibility issues. At 10 MHz due to low time periods these idle time becomes small and they limit to a small value. 1MHz TCK waveform: Sluggish rise in TMS due to internal pullups are above 1V in this waveform 10 MHz TCK waveform: Sluggish rise in TMS is limited either by internal controller drive or low time window Question: Is the pull resistor is really required or what is reason for pull up in TMS line with CJTAG operation? Do we have any standard time, where the both the TS and debugger can leave the Bus idle? Why TCK waveform has this different on time and off time in single time period at high frequencies refer image 2?