LTV

The problem was the lwIP and the AxiDma interrupts interracting. See this Xilinx thread for details: https://support.xilinx.com/s/question/0D52E00006iHxBYSA0/lwip-interrupt-setup?language=en_US

Hi, I am using the LwIP echoserver example on Zybo and trying to send some commands from a PC running Python to Zynq via the recv_callback() function in the echo.c. Inside the recv_callback(), i call an AxiDma transfer. Something like this: //inside recv_callback() in echo.c strncpy(command, p->load, p->len); if( strcmp(command, "startAxiDmaCmd") == 0) { startAxiDma()// call the start AxiDma function tcp_write() //write ack to PC } The AxiDma functions makes one transfer, and returns as it should. Consecutive transfers are done by the DMA Interrupt handlers. That is a simple register mode for AxiDma with Interrupts. The transfer take some time 6-7 seconds for 512MB in 32MB chunks/transfers so i have 16 transfers total. The problem is that after the Dma transfers are done- all 16 transfers, my echoserver no longer, calls back the recv_callback(), when i initiate another command from PC (any command dma or not ), The PC socket responds with TimeoutError " A connection attempt failed because the connection party(Zynq that is) did not properly respond after a period of time" --it seems that the prolonged AxiDma Interrupts are messing up the echoserver TCP stack. Dont know exactly how? I know that the echoserver uses timer interrupts for transmit. bit it happens on receive. DMA transfers work by themselves, echoserver also work by itself ( looping back simple commands) but when combined -not Does anyone know how to fix that?

How can I get the Gerber (or ODB+) files for that board (Genesys ZU-3EG REV B )and /or information on net lengths matching from Zynq to the FMC connector? Thanks