John J

Hi @Richm, I apologize for not getting back to you sooner. I'm currently on travel. I did follow the Xilinx tutorial noted above for creating a platform project and adding the application. This crated projects with a different structure, but gave me the same error. I have not checked if it occurred the exact way as the other projects. I'm targeting the Ultrascle+ 5EV on the Genesys Zu board. I did check the generate boot components. Yes, I do build the platform first or do a build all. I get the same result either way. I believe that both domains are created, but I will have to verify that when I have access again. Thank you for your help. any suggestions would be appreciated.

Hi @JColvin, I would appreciate any help you can provide. I also tried separate steps of creating a platform project and application project, as per the following steps from Xilinx. This produced the same result. This method produces a project structure more like the Digilent Hello World project, but produces the same error. https://xilinx.github.io/Embedded-Design-Tutorials/docs/2021.1/build/html/docs/Introduction/ZynqMPSoC-EDT/ZynqMPSoC-EDT.html Thank you for your help. John J

I am getting the following error when debugging a newly created Vivido/Vitis bare metal "hello world" project using the steps below. I am just following tutorials by Digilent and Xilinx. I've seen other posts with the error, but I have not yet found a solution. I get the following error. 10:00:24 INFO : 'bpremove $bp_0_22_fsbl_bp' command is executed. 10:00:24 INFO : Context for processor 'psu_cortexa53_0' is selected. 10:00:24 INFO : Processor reset is completed for 'psu_cortexa53_0'. 10:00:24 ERROR : Memory write error at 0x0. Cortex-A53 #0: EDITR not ready The Digilent supplied "hello world" project works, but I have to create a soft link the FSBL in the correct place to make it go. If I replace the FSBL in my project with the one from the Digilent supplied "hello world" projecct, debugging the application works. Here is what I did to create the Vivado and Vitis projects: Development Environment: Vivado/vitis 2021.2 running on Ubuntu 20.04 Board: Genesys-ZU-5EV Rev. D Board files: genesys-zu-5ev/C.0/* (https://github.com/Digilent/vivado-boards/tree/master/new/board_files, Aug 10, 2021) Constraints file: Genesys-ZU-5EV-D-Master.xdc (https://github.com/Digilent/digilent-xdc, Jul 20, 2021) Vivado Create a top-level project directory Start Vivado Create a project in a subdirectory under the top-level directory Select the project type as an RTL project Skip the “Add Sources” step Under “Add Constraints” step, add the Genysis-ZU-EV5 constraints file and enable the “Copy constraints file into project” option Select the boards tab and select the Genysis-ZU-5EV board Create a block design and name it like ProjectName_bd Add a Zynq_Ultrascale+_MPSoC to the block design Run block automation with the default settings Connect pl_clk0 to both maxihpm0_lpd_aclk and saxihpc0_fpd_aclk Under the Sources tab of the block diagram, open the constraints file in the editor and uncomment the firs two lines that start with “set_property” Under the Sources tab, select the block design file and create an HDL wrapper Click on Generate Bitstream and click through the dialogs Under the File menu export hardware Include bitstream Export the hardware as an XSA with bitstream Vitis Start Vitis Create an application Create platform form XSA file Select the hello world template Build it Debug single application