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qamesh
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Posts posted by qamesh
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On 8/22/2016 at 9:07 PM, D@n said:
I also connected this 50 ohm resistor to each terminal (P terminal and N terminal ) exactly as it looks in the attached photo , but I was not able to see anything on the oscilloscope . I think it is not a problem in the code itself. The simulation shows that there is an output signal.
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Hello,
Hi, I am experimenting with differential outputs on the Arty A7. For this, I am using the 100MHz clock and have instantiated an ODDR then OBUFDS -- . I Have also looked through the 7-series Select-IO Resources User Guide and the only differential I/O at 3.3V is TMDS_33 IOStandard.
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKADC(
.Q(buff_local),
.C(buff_in),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(1'b0),
.S(1'b0)
);
OBUFDS #(
.IOSTANDARD("TMDS_33") // Specify the input I/O standard
)OBUFDS_inst (
.O(buff_out_p), // Diff_p output (connect directly to top-level port)
.OB(buff_out_n), // Diff_n output (connect directly to top-level port)
.I(buff_local) // Buffer input
);
The .xdc file has the following --
## Pmod Header JB
set_property -dict { PACKAGE_PIN E15 IOSTANDARD TMDS_33 } [get_ports { buff_out_p }];
set_property -dict { PACKAGE_PIN E16 IOSTANDARD TMDS_33 } [get_ports { buff_out_n }];
Pins E15/E16 are HR I/O banks [JB1/2] and they should work fine.
Synthesis & implementation are fine and I can generate a bitstream, but I see no output on these pins (just 0v)
I also tried to connect a termination resistor of 50 ohm pulled up to 3.3 V as recommended for FP_3.3_50 [OFF chip termination]. but it gives nothing...can anyone help me in this? -
@jamesWHello , I am currently facing the same issue and Would like to ask the size of the termination resistor in your case?.. as I see in the Manual E15/E16 have zero internal resistor in series, did you connect any other resistor in series externally?
regards
Differential outputs on Arty-A7 board with TMDS
in FPGA
Posted · Edited by qamesh
@asmiThank you for the offer.
I went with the project as simple as possible , where I only take a clk signal from a Clock Wizard and route it out as a differential output but even this didn't help. The other module top_led_test is just a counter that I check the status of the board through it by connecting it to one of the leds
top.vhd top_led_test.v