[VGA resolution with PCAM & Zybo z7]

Hello,

 

I'm trying to obtain VGA resolution 640x480 at 30fps with Zybo-Z7 Digilent demo project. The project run smooth with the HD resolution but I need 640x480. I patch 720p60fps preset{

        //[7:4]=0010 System clock divider /2, [3:0]=0001 Scale divider for MIPI /1
        {0x3035, 0x11},

        //[3:0] Output horizontal width high byte
        {0x3808, (640 >> 8) & 0x0F},
        //[7:0] Output horizontal width low byte
        {0x3809, 640 & 0xFF},
        //[2:0] Output vertical height high byte
        {0x380a, (480 >> 8) & 0x7F},
        //[7:0] Output vertical height low byte
        {0x380b, 480 & 0xFF},

}

I used the existing R640_4860_60_NN timing_t struct I just change the polarity to positive as my device need. But it doesn't works.

Is someone could provid a working preset ?

Thanks by advance.

Regards

[Mipi-csi2 rx subsys tvalid condition]

5 hours ago, thinkthinkthink said:

We were working on a demo project for zynq ultrascale+ with the MIPI CSI RX Subsystem however it got postponed indefinitely. But you can check out Adam Taylor's own demo for our Genesys ZU board, he is using it in his block design.

Thank you for your reply. I've check the A.Taylor's Mipi CSI-2 Rx SubSys config and we have the same parameters except for the lane rate I use 336MBP and he used 280MBPS. A.Taylor's SW project use one config 720p*1280 @ 60fps,  A.Taylor's cam SW init config is the same than Digilent.

The main difference is I config iic cam from PCIe without µBlaze. I readback cam register from iic and it looks ok.

5 hours ago, thinkthinkthink said:

As for why some of our IPs are disabled when adding them to your project's IP Repository there could be multiple answers. What board is your project set to target ? I know for a fact our MIPI IPs are NOT compatible with the zynq ultrascale+ architecture so they're greyed out for me too when trying to add them to a Genesys ZU project.

Or maybe when the source files were packaged into IPs, compatibility for Kintex7 wasn't added. However, I'm pretty sure our MIPI IPs work great on Kintex7 too, we have a FMC-Pcam-Adapter demo project for the Genesys2.

What you can try is to open your Zedboard project, right-click on the IPs that are disabled elsewhere, go to Edit in IP Packager and press OK. It will open a new vivado tab, go to Compatibility and click on the "+" button and choose Add Family Explicitly....

From there you can selectto add the Kintex7 (Kintex-7) family to IP compatibility, just be aware that our MIPI IPs don't work on ultrascale and ultrascale+ families.

You are right Kintex 7 compatibility wasn't added in IP packager. I could instantiate it after add.

Quote

And that should be it, also make sure to check our Genesys2 FMC-Pcam-Adapter DEMO too, it might literally be exactly what you need for your KC705 board. Here's the wiki page (don't let the un-updated photos fool you). 

If I cannot have valid frame with my project I will try to adapt the Genesys2 project to KC705.

Thank's for your detailed explanation.

Regards

 

 

[Mipi-csi2 rx subsys tvalid condition]

Hello,

I'm facing the same problem I'm using Xilinx Vivado 2020.1 IP. When I'm trying to import Digilent IP Mipi-CSI & D-PHY are grayed out:

I can open them from Zedboard-HW.xpr but not from import in my project. Is there a whay to do it?

Regards

[Mipi-csi2 rx subsys tvalid condition]

Is it planned by Digilient to update demo with Mipi-csi2 rx sub-system, this IP being default Mipi IP since Vivado 2020.1?

Regards

[Mipi-csi2 rx subsys tvalid condition]

Hello, 

I'm using "Mipi-csi2 rx subsys" on KC705 & 0V5640 with FMC Digilent adapter. I obtain data from d-phy (fig1) but I can't obtain TVALID signal from AXIS output.

Mipi-csi2 rx subsys is set to decode YUV422 10 bit signal, on 2 Lanes with LaneRate to 280Mbps.

I modify the Xilinx cfg_init tab from 0V5640.h and set register:

{0x3034 || 0x1A} 10bit 

{0x300e || 0x45 } MIPI enable || Two lane mode

{0x4800 || 0x14} [5]=0 Clock free running, [4]=1 Send line short packet, [3]=0 Use lane1 as default, [2]=1 MIPI bus LP11 when no packet; Default=0x04

{0x4300 || 0x30}  Format Control (YUV)

Edit: I read from ISR=0x00022882: bit2-ErrFrameSync VC0=1 | bit7-ErrFrameSync VC3=1 | bit11-ECC 2-bit error | bit13-SoT error detected bit17-StopState

Q0 How to set 0V5640 register 0to obtain valid frame with YUV10bit config?

Q1 Which condition are needed to generate tvalid on axis output?

Q2 Is there register to set to generate axis transaction from  "Mipi-csi2 rx subsys"?

Regards.