Hi Digilent's engineer,
When I use Digilent audio demo(https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-dma-audio-demo/start) I find that it dose not work at Vivado 2019.1/2018.3. The bitstream can be generated successfully, and the C file in Xilinx SDK runs well, but I find that it cannot get audio data, so recording can never be done, also I find that it can be run well at Xilinx Vivado 2019.2/2020.2 and VITIS 2019.2/2020.2, but I must use Vivado 2019.1 and Xilinx SDK because of Cortex M3 IP. I must find out why system dose not work at Vivado 2019.1 , but everything seems like no error here.
Thanks a lot!
