[Driving differential output signals on Cora Z7]

15 hours ago, zygot said:

The naming convention for Xilinx tools in regard to differential signals is "<name>_p", "<name>_n". The tools are sensitive to this convention. But this isn't your only problem. You are assigning single-ended IOSTANDARD LVCMOS33 to pins that you intend to be differential. But, that's likely not the biggest problem. The only differential IOSTANDARD for pins on IO banks powered by 3.3V is TMDS, which requires external 50 ohm terminators to ground.

Before trying to do a design using a particular logic standard you need to understand the capabilities and limitations of the device. For Xilinx Series 7 FPGAs almost everything that you need to know is in the ug471_7Series_SelectIO Reference Manual. This is no different than trying to use any electronics componet; it's just that FPGA devices are a bit more complex.

It's unfortunate that FPGA board vendors are confusing customers by implying that their products can support differential signalling when, by design, they can't. Digilent isn't the only one doing this. To my knowledge the ATLYS is the only FPGA board sold by Digilent that has a PMOD connected to and IO bank that can be driven by a user selected Vccio compatible with differential signalling IO other than TMDS. The FMC equipped boards do provide this, but only for the FMC pins. Even the CMOD product line only offers 3.3V IO.

If you want to use a PMOD pin to drive or receive differential signals then your best option is to use en external differential driver/receiver device that converts differential signals to single-ended 3.3V signals and visa versa.

So how many years is it that I've been trying to get Digilent to allow their customers the freedom to use Xilinx FPGAs to their full capability to no avail? Well, they do have 2 SYZYGY capable FPGA platforms that do this. Unfortunately, not all users are able to design custom SYZYGY pods. Connecting external interfaces to high density SMT connectors is beyond the capability of most FPGA board users.

There really isn't a good excuse for not providing at least one 2.54mm or 2mm header with pin connections suitable for differential signalling so that customers can at least experiment with it. Ultimate performance isn't so important and is unlikely to be achieved anyway unless the FPGA has HP IO banks and internal termination options.

 

Okay I understand now. TMDS will actually suite my needs so only having a 3.3V bank is fine. I had tried using it before but I wasn't aware of the required pull-up resistor.

Also, I actually was assigning my output pins to use LVDS_25, I just copied the wrong lines into my post.

Thanks for your response!

 

[Driving differential output signals on Cora Z7]

Hello,

I'm trying to output a differential signal using the PMOD pins on my board. My attempts so far have been unsuccessful.

I just have a simple test set up which creates a differential clock signal using the Verilog shown below.

module top
(
  input clk,
  output clk_test,
  output clk_test_n
);

generate
    OBUFDS #(.IOSTANDARD("LVDS_25")) obufds_test(.I(clk), .O(clk_test), .OB(clk_test_n));
endgenerate

And I map these signal to two PMOD pins.

set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { clk_test }]; #IO_L8P_T1_34 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { clk_test_n }]; #IO_L8N_T1_34 Sch=jb_n[1]

The documentation talks a lot about inputting differential signals but nothing about driving them. Is this possible?