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Lio

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Posts posted by Lio

  1. Hi all,

    I have created a block design in vivado,and generate bitstream successfully.Everything seems to be successful,and then i export hardware and create an application project with "Hello world" template,and i did not change anything. 

    But when i try to program FPGA, i get the following error messages.

    1509884a021cd5cd2e3bd6c17809f5e.png.423450ab1af133e9d006018d47264991.png

    " ERROR: [Updatemem 57-153] Failed to update the BRAM INIT strings for ./.../*.elf and ./.../*.mmi "

    image.png.2562f7d71d7d541a62881bb06883fc4a.png

    I'm pretty sure that i have selected the bitfile that was generated earlier.

    image.png.906affb7f3c30749835d2faba47fc525.png

    And here is my block design ,any suggestions?

     

     image.thumb.png.11288b4a1e52399300c1abc9a15a7aa1.png

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