[SREC SPI Bootloader not working]

Right, so interestingly enough just after posting I found this thread... 

It points to an ELF bootloader on Github (https://github.com/henrikbrixandersen/elf-bootloader), I downloaded that and added it to my project (removing the SREC SPI loader) and it just works!!

 

I had a slight issue with Vitis where it simply would not let me flash a raw .elf file, it says its a valid file to use when flashing, but then it kept complaining about a missing .bin file, so as the ELF bootloader wants a raw elf file with the '.ELF' header in the hex code I simply took the application.elf file and renamed it to application.bin, then Vitis programmed the SPI flash with that file in the location requested and now it works!

 

It is also a bit smaller than the SREC loader (10kB with heap & stack vs 17-18kB with heap & stack). If I can get rid of the heapt & stack and have it still work I may even be able to reduce the BRAM on my MicroBlaze down to 8kB.

 

Something isnt right with either the SREC SPI Bootloader or in the way Vitis is converting the .elf into SREC it seems. I have noticed the SREC file is only ~634kB where as my ELF file is 1,134kB! Could it be something to do with that??

 

HOWEVER...it does still take 25-30 seconds from power on to configuration completing (config itself is very quick, its about 23-24 seconds before the bootloader even starts doing its job), is there any way to speed that up?

 

Also, when I reset the MicroBlaze using a push button the bootloader does not re-start and re-program the DDR memory with my application, so I need to reprogram the entire FPGA using the 'PROG' button the the Nexys Video. Any ideas on why the bootloader doesn't reset when I reset the MicroBlaze? I have noticed the reset works fine with my application on its own or with the SREC SPI Bootloader, just not with this ELF Bootloader I found??

[SREC SPI Bootloader not working]

Hi all, I am trying to get my project to boot directly from flash memory, but as requires a lot of BRAM, I am trying to use a bootloader to load up the application and run directly from the DDR memory I have.

 

If I dont use a bootloader and run my application directly from MicroSD it works fine, but then needs a lot of BRAM and as I want to move this to a smaller FPGA later on a custom board I need to reduce the BRAM utulisation and to do that I need to run from DDR and use a bootloader.

 

So far I have done the following...

 

1. Created HW design in vivado with QSPI IP on a 50MHz clock at ext_spi_clk and generated bitstream
2. Created my SW application in vitis and assigned all to DDR
3. Created a new application in vitis for the bootloader and assigned all to BRAM
4. Configured the blconfig.h to look for my application at 0xA00000 (10MB into the 32MB of QSPI)
5. Built all and generated a bootloader.elf as well as my application.elf
6. Generated a download.bit file using my project.bit, project.mmi and bootloader.elf (download.bit size is 9.5MB)
7. Programmed the download.bit file to QSPI via "Xilinx -> Program Flash" at offset 0x0 (no offset)
8. Programmed the application.elf at 0xA00000 as per the definition in step 4

When I do the above I get the info below in the Vitis Serial Terminal:

[quote]SREC SPI Bootloader
FlashID=0x1 0x2 0x19

Loading SREC image from flash @ address: 00A00000[/quote]

Then nothing happens! I assume the bootloader is seeing the flash as it shows a flashID not equal to 0!

I have read back the .bin file from the QSPI device and can see there is data that begins at 0x00A00000 (see image attached), so not sure what is going on, any ideas? Also attached a snippet of how I have the QSPI IP configured.

 

This is on a Digilent Nexys Video dev board with Artix-7 XC7A200T FPGA.

 

[Xilinx VPSS MicroBlaze Example]

So, I decided to side-step a little...my HW is VERY similar to what is on page 69 of the product guide (link below), as such I thought it would maybe be best to use the example code described in there from page 71 onwards. Only difference is I have an AXI traffic gen connected to the TPG to output a fixed pattern at fixed resolution, so I commented out the code for all the TPG stuff in the example and went to build it but not I keep getting the error "unknown type name Xperiph" and I am not sure why when that's part of the example code that relates to things like the VTC which I do have and I also have connected in the same way as them.

The Vitis side of Xilinx stuff is really not my strong suite, embedded C and all that, especially their implementation of it.

https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/v_proc_ss/v2_3/pg231-v-proc-ss.pdf

[Xilinx VPSS MicroBlaze Example]

Quick follow up...someone on the Xilinx forum pointed me towards the Video Series Blog... https://support.xilinx.com/s/question/0D52E00006hpsS0SAI/xilinx-video-series-and-blog-posts

It looks like "Video Series 29" is closest to what I need. I have downloaded the files but when I try to build the SW project I kept getting errors about missing headers.

I added the "Includes" to the header file sources in the Xilinx Vitis directory, but now when I try and build I keep getting errors like the ones below and I don't know what to do to fix it, any suggestions?

../src/app_hdmi.c:111:15: error: 'XPAR_AXI_VDMA_0_BASEADDR' undeclared (first use in this function); did you mean 'XPAR_AXIVDMA_0_BASEADDR'?
 
../src/app_hdmi.c:260:26: error: 'XPAR_CLK_WIZ_0_BASEADDR' undeclared (first use in this function); did you mean 'XPAR_GPIO_0_BASEADDR'?
 
../src/app_hdmi.c:451:51: error: 'XPAR_V_TPG_0_DEVICE_ID' undeclared (first use in this function); did you mean 'XPAR_XV_CSC_0_DEVICE_ID'?
 
../src/app_hdmi.c:459:46: error: 'XPAR_V_TC_0_DEVICE_ID' undeclared (first use in this function); did you mean 'XPAR_XV_CSC_0_DEVICE_ID'?

I just want to get this build working so I can use it as a template to modify and suit my own needs. Any help greatly appreciated!

[Xilinx VPSS MicroBlaze Example]

Hi all,

I am looking for a Microblaze (or at least some kind of Vitis) example project for the Xilinx Video Processing Sub-System.

Really what I am looking for is something like this video with the sample code... https://www.youtube.com/watch?v=tBb1iL6lb24

If you skip to 8:20 in the video you will see that there is a menu which allows you to simply set the output resolution / scaling, that is all I am needing for now.

I have a test pattern generator running as part of the block design and I have implemented the IP cores for VPSS, MicroBlaze, MIG_7 memory controller, etc. Now I just need an example MicroBlaze code to do the above.

Any suggestions?

[Applications of FPGA vs GPU?]

if you have the first 24 bytes, that means out of your 256 bits you still have 64-bits unknown. The RC5 distributed computing network took almost 5 years to brute force a 64-bit encryption according to this article... https://blog.codinghorror.com/brute-force-key-attacks-are-for-dummies/

 

A single FPGA or even a small cluster would likely take much longer.

[Digital Discovery - Using Signal Generator & Logic Analyser Simultanously]

Perfect, thanks! ?

[Newbie to intermediate training online anywhere? Nexys a7 prefered.]

3 hours ago, twinvalleytech said:

Thanks for the replies Mario875 and thinkthinkthink.  I actually had watched all of Knitters videos and hope more will be on the way.  I checked out the book and will see if I can find it here in the states.

Is the smart money on going with a basys 3 or should I go with a nexys a7 or even the soc board that the knitter uses in her videos?    I can afford any of them, so if it was you, what would you go with to follow up after working with the lattice based nandland board?

In terms of going for the SoC board, that depends if you will have a use for a dedicated ARM hard core processor. Will you have applications that will make use of it or are you solely focused on FPGA development?

If you only care about FPGA development and want to go between the Basys 3 or Nexus A7 along side that book I recommended, honestly, as the saying goes "buy cheap, buy twice". The Basys 3 is a fantastic board, but the Nexus A7 can do everything the Basys 3 can do and more. The Nexus A7 has RAM and an Ethernet Port that the Basys 3 does not and that is where the book calls up the use of the Arty A7. However the Nexus A7 also has the 7-segment displays that the Basys 3 has that the Arty A7 does not.

So if you decide to get that book and read it cover to cover, then the Nexus A7 should be a "1-stop shop" board that you can use throughout the entire thing. However it is worth noting that the Arty A7 board is only really required for later chapter, the Basys 3 can do everything needed for most of it.

When following the book you just have to be aware that if you are using the Nexus A7 the constraint files and setting up of the board in Vivado will be different, but as long as you are somewhat familiar / savvy with these already from your previous experience of FPGA's that should not be an issue.

[Newbie to intermediate training online anywhere? Nexys a7 prefered.]

This book is a great start. It begins with what logic gates are and builds upon that. From a basic LED being turned on and off with a switch all the way to implementing a soft core CPU on an FPGA and beyond.

The book is to be used along side the Basys 3 or Arty A7 dev boards, but honestly, I would opt for the Basys 3 for this book as most of the early chapters are geared towards that board more so than the Arty A7.

Everything taught in here is transferable to all other FPGA's. The book covers both Verilog and VHDL simultaneously, but I would only chose to learn 1 language first and skip everything related to the 2nd language for now, you can always go back and learn it later. It is however slightly geared more towards Verilog than VHDL, but all examples and exercises are shown in both languages.

https://www.amazon.co.uk/Digital-System-Design-FPGA-Implementation/dp/1259837904

[Digital Discovery - Using Signal Generator & Logic Analyser Simultanously]

Hi All,

Question is pretty much in the title, can someone confirm, is it possible to use the Digital Discovery signal generator function at the same time as using the logic analyser function?

I am wanting to inject a signal into a device (any 1.8V signal will suffice for my testing at the moment) and then monitor the data that gets output at the other end.

If the Digital Discovery can perform these functions simultaneously then it would be ideal.

Thanks

[Cmod A7 Vivado 2021.1 Place 30-574 error]

Not much you can do other than edit the constraints file as Vivado is basically saying the pin you’ve selected that the LED is connected to is in a bad place for routing of the clock and could be optimised by using a more suitably placed pin on the FPGA. Unfortunately as it’s a dev board the LEDs and what not are connected to the pins chosen by digilent and you can’t change that, just add the line of text to your constraints file or chose a different LED that may be connected to somewhere Vivado prefers.

 

Also, the solution was given to you by Vivado, there was no need to search the forum to find it ?