Golan Asher Audiopixels

Hi, I have two cards of ARTY-S7-50 Rev B. I can not power up these cards when I connect power supply of 12v 3A to J12. I can power up these cards, when I connect USB cable to J10 (Micro USB Plug on card), but I want to use J12 with using power supply of 12v for power up. The same power supply of 12v, 3A I am using for other card successively, ARRY-S7-50 Rev E. So I suppose the problem is not the power supply, but the card Rev B. I tried 3 options with Jumper JP13: REG, USB and without Jumper. With all 3 these options, I did not succeeded to power up my cards, Rev B. Attach pitchers of one of my Rev B cards. Can you suggest a solution to that problem ?

In the original design, that UART is operate OK, I am using : TTL-232R-3V3, USB to TTL Serial Cable (3.3V), that includes FTDI Chip. I checked I/O report after implementation, and saw that new I/O pins of RXD, TXD are as expected after modify it the the constraint file. Still, when using USB cable to J10 (Micro USB), on ARTY-S7, UART do not operate.

I am using Windows 10 Pro Version 21H2 The original UART design I am using was operating OK with AXI UART lite connected to IO9, and IO10, of connector J2 of ARTY-S7. But when I modified FPGA pins to pins of UART to USB (V12 and R12 pins of FPGA), The UART stopped operating. The modification was only in XDC file (I/O constraints of Xilinx). I am also using in VIVADO, definition of Board (ARTY-S7-50), and P/N of FPGA (XC7S50-1CSGA324C). Maybe, because of that definition, of Board, the "UART-USB" is not operating...

Hi, Still I do not know how to solve this problem.

I am using UART in my design with UART, IP of XILINX: uart_axi_lite. This IP of UART has two pins: "uart_tx" - output from FPGA, and "uart_rx" - input to FPGA. In .xdc (constraint file), i wrote: set_property PACKAGE_PIN R12 [get_ports uart_tx] set_property IOSTANDARD LVCMOS33 [get_ports uart_tx] set_property PACKAGE_PIN V12 [get_ports uart_rx] set_property IOSTANDARD LVCMOS33 [get_ports uart_rx] I also use in VIVADO project Board definition, which contain: Board UART, see picture attach. Maybe, the problem is two UARTs, (as you wrote me, that i see COM6, COM7). Do you have idea how to cancel the "Board UART" ?

I am using ARTY-S7-50. I am using UART in FPGA Design. I connected UART RXD of FPGA Design, input to FPGA, to V12 PIN of FPGA, UART_TXD_IN I connected UART TXD of FPGA Design, output from FPGA, to R12 PIN of FPGA, UART_RXD_OUT I installed "Virtual Com Port", CDM212364_setup.exe from: https://ftdichip.com/drivers/vcp-drivers/ I saw in my computer, at "Device Manage", two new coms: COM6, COM7. I configured COM6, COM7 to Baud rate of 460,800, as suit to UART Rate in the FPGA design. I sent by :Real term" terminal, command that FPGA should accept and reply answer, but i did not get any response. Attach pictures of "Device Manager". I tried COM6, and COM7, without success. In earlier FPGA Version, I used other different IO's for using UART, IO9 (pin T15, for FPGA_UART_TX), IO10 (pin H16, for FPGA_UART_RX), and using successfully "Real term" terminal, command that FPGA should accept and reply answer, i got all responses i accepted. Can you help ? What should i do to operate the USB to COM ?

Thanks. Golan Asher.

What are the differences between Schematic ARTY-S7-50 E1 and E2 ?

What are the differences, between Revision E.2 and E.1 (of ARTY-S7-50) ?

Hi, I read in your document: ArtyS7 FPGA Board Reference Manual, at chapter: DDR3 Memory: For clocking, it is recommending that the System clock be set to “Single-ended” and connected directly to the onboard 100MHz oscillator on pin R2. The Reference clock should be set to “no buffer” and can be connected to a 200 MHz clock generated from a clocking wizard elsewhere in the design So in that case, as I understand, the signal DDR3_CLK100, that connected to PIN of FPGA: R2, connected directly in the FPGA to sys_clk of MIG (and not using DCM with distributing clocks). What clock should I use to other logic in my design ? I understand also that you took off from mounting the additional oscillator in the card, signal name: UCLK, that connected to F14 of the FPGA. It is also written in Schematic: "No Load". Do I need to mount that Oscillator ? (IC2) or do you have other solution ? arty-s7_rm.cleaned.pdf

Hello, Do you have in your web, Vivado project contain MIG, DDR interface, that works well on the board of Digilent: ARTY-S7 (with Spartan7, S50|) ? If yes, can you send link, that i can download it ? Regards, Golan Asher.