[A Guide to Using DDR in the all HDL Design Flow]

@zygot

Thank you for compiling my ddr test project. If I make the changes you pointed out it seems to work without errors or warnings. Also I got the best timing so far when I included my application (that is using ddr) into the design. However I feel that it is a lost cause, as you pointed out, xc7s25 is small and ddr functionality almost takes up the whole thing :O. It will probable be impossible to get the speed I need out from the thing. Anyway, thanks again taking the time to help me!

[A Guide to Using DDR in the all HDL Design Flow]

@zygot, Ok, I have checked but I did not see anything wrong with variable name or constraint file. I remade the whole thing again, in case I made some mistake but I get the same result and the same error.

You can find the whole vivado project here.

[A Guide to Using DDR in the all HDL Design Flow]

Hi again @zygot

Thanks again for helping out.

I do not get a warning if I just use the 100Mhz clock directly with MIG. I only get a warning about sub-optimal placement if I call clock generator IP first.

So basically this works:

    example_top u_example_top
    (
     .ddr3_dq(ddr3_dq),
     .ddr3_dqs_n(ddr3_dqs_n),
     .ddr3_dqs_p(ddr3_dqs_p),
     .ddr3_addr(ddr3_addr),
     .ddr3_ba(ddr3_ba),
     .ddr3_ras_n(ddr3_ras_n),
     .ddr3_cas_n(ddr3_cas_n),
     .ddr3_we_n(ddr3_we_n),
     .ddr3_reset_n(ddr3_reset_n),
     .ddr3_ck_p(ddr3_ck_p),
     .ddr3_ck_n(ddr3_ck_n),
     .ddr3_cke(ddr3_cke),
     .ddr3_dm(ddr3_dm),
     .ddr3_odt(ddr3_odt),
     .sys_clk_i(sys_clk_i),
//     .clk_ref_i(clk200),
     .tg_compare_error(tg_compare_error),
     .init_calib_complete(init_calib_complete),
     .sys_rst(sys_rst)
     );

 

But this does not:

clk_gen clk_gen_inst (
    .clk_out1(CLK_40Mhz),
    .clk_out2(CLK_200Mhz),
    .clk_out3(DDR_CLK),
    .resetn(rst_n),
    .clk_in1(sys_clk_i)
    );

    example_top u_example_top
    (
     .ddr3_dq(ddr3_dq),
     .ddr3_dqs_n(ddr3_dqs_n),
     .ddr3_dqs_p(ddr3_dqs_p),
     .ddr3_addr(ddr3_addr),
     .ddr3_ba(ddr3_ba),
     .ddr3_ras_n(ddr3_ras_n),
     .ddr3_cas_n(ddr3_cas_n),
     .ddr3_we_n(ddr3_we_n),
     .ddr3_reset_n(ddr3_reset_n),
     .ddr3_ck_p(ddr3_ck_p),
     .ddr3_ck_n(ddr3_ck_n),
     .ddr3_cke(ddr3_cke),
     .ddr3_dm(ddr3_dm),
     .ddr3_odt(ddr3_odt),
     .sys_clk_i(DDR_CLK),
//     .clk_ref_i(clk200),
     .tg_compare_error(tg_compare_error),
     .init_calib_complete(init_calib_complete),
     .sys_rst(sys_rst)
     );

 

[A Guide to Using DDR in the all HDL Design Flow]

@zygot Thanks for clearing that up. I understand what you are saying. but..

When I read the recommendations from digilent they want me to use the 100Mhz clock for driving the DDR3.
https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty-s7_rm.pdf

This can be found on a MMCM capable pin. If I use it as you do in your tutorial I get this error:

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:  
ddr3_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and sys_clk_i (LVCMOS33, requiring VCCO=3.300)

And if I use the SSTL135 I get:

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

Oscillators can be found on sheet 4 and 5.
https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_e.pdf

(DDR3_CLK100 1.35V 100Mhz)

(UCLK 3.3V 12Mhz)

You mean that I should use the 3.3V 12Mhz instead of 100Mhz 1.35V? Or should both work with DDR3 on my board you think?

 

[A Guide to Using DDR in the all HDL Design Flow]

Hi again,

Had some time to look through this again. Looking at the first tutorial.

I see that you have this clock in your project:

set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports sysclk]

This clock you can later generate the clocks you need (clk_out1 and clk_out2);

   clk_wiz_0 instance_name
   (
    // Clock out ports
    .clk_out1(clk100),     // output clk_out1
    .clk_out2(clk200),     // output clk_out1
    // Status and control signals
    .reset(0), // input reset
    .locked(locked),       // output locked
   // Clock in ports
    .clk_in1(sysclk));      // input clk_in1

 

I think one problem for me with arty s7 board is that I cannot use LVCMOS33. I need to use SSTL135 for my clock (while the rest of my design is 3.3V logic). The DDR for my board runs on bank 34 fed with 1.35V. 100Mhz oscillator also runs with same voltage naturally. Can this make timing more difficult for me? Or am I misunderstanding something?

[A Guide to Using DDR in the all HDL Design Flow]

Thanks for the post! I have read through all your tutorials but I have not tried the examples/demo yet. I will do that in the coming weeks to learn more.

I have the ARTY S7 board by digilent and I have a question regarding the clocking.

My design is a graphic converter. It takes input from ADC and creates HDMI output. DDR memory is meant to be used as frame buffer.

My application need a 200Mhz and 40Mhz clock. For the DDR to work I need 100Mhz sys clock and 200Mhz ref clock. On Arty board there is a 100Mhz oscillator connected to R2. What I would like to do is to use MMCM to generate all the clocks I need from the 100Mhz. In other words I want to do the same thing you do in your first tutorial. But whatever I try, I always end up with timing or placement problems (see attached for one example).

Do you have any recommendations for how I should handle my clock situation?
I have seen that there is a ui_clk coming from the ddr infrastructure, is this what I should use?
I see that you are using it in your second tutorial, but I have a hard time understanding VHDL code.

 

one_example_of_problems_I_have.txt

[Examples of using the DDR3 on ARTY S7 board]

8 hours ago, zygot said:

A sure way to introduce timing issues is by failing to properly handle signals crossing clock domains.

Did you see my DDR tutorial ?
https://forum.digilentinc.com/topic/22197-a-guide-to-using-ddr-in-the-all-hdl-design-flow/
 

No, I did not see your tutorial. Thanks a lot for taking the time to create it!
I will check it out, it will help me a lot for sure.

 

[Examples of using the DDR3 on ARTY S7 board]

On 10/2/2021 at 12:02 AM, JColvin said:

Hi @Mathias

The instructions are long mostly because they are written to be fairly verbose and (ideally) clear.

Vitis should not be that big to install; or at least when I use the self-extracting web installer and only leave board options that I need checked, the final disk installation size of both Vivado and Vitis 2021.1 for me is just shy of 70 GB. Makes me yearn for the less than 15 GB size that 2015.4 was to be sure, but that's neither here nor there.

I asked another co-worker to make a DDR demo and they're hoping to get it completed in the next couple of weeks (in between all of their other tasks and making sure the documentation/tutorial aspect is clean).

Let me know if you have any questions.

Thanks,
JColvin

Hi,

What is the status of this? Any demo I can take a look at yet?

In the meantime I have tried to use the MIG to generate code and I think I've got something to work with. I looked at "Arty S7™ FPGA Board Reference Manual" in the "DDR3L Memory section":

https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty-s7_rm.pdf

and in xilinx documenation in "DDR3 SDRAM Memory Interface Solution":

https://www.xilinx.com/support/documentation/ip_documentation/ug586_7Series_MIS.pdf

With a lot of effort and after a lot of trail and error I can now make implementation and meeting timing constraints (Worst negative slack: 0.341 ns) for the DRAM only project. If I look at the "device" tab I see that DRAM implementation takes up a lot of space on the fpga already.

 

And the thing is, as soon as I start to use the DRAM I cannot meet the timing constraints any more. Not by a long shot (Worst negative slack: -8.982). I have attached the timing report.

It seems that I am forced to use the 100Mhz clk on the board to the DRAM implementation and I cannot use it for anything else. If I try to, I get "sub optimal" errors and/or placement errors. So for the implementation that is actually using the DRAM part must use another clock. So I use the 12Mhz for that. I think this makes things worse, timing wise...

Any suggestions? An example would of course be best so I can have a look if I have done something wrong.

Regards,
Mathias

timing_report.zip

[Examples of using the DDR3 on ARTY S7 board]

Hi JColvin,

Thanks for the information. Would appreciate any files of any kind that I can use to better understand how to use the dram. Seems vitis needs almost 170GB to install, yikes. The instruction you refer to is about 50 steps to follow, I wish it was more simple, but thanks for the help anyway :)

Regards,
Mathias

[Examples of using the DDR3 on ARTY S7 board]

Hi Zygot and thanks for answering this question. Never before did I have this kind of problem, perhaps only in the FPGA world this can happen.

I simply want to read and write from/to memory. Don't need to be that fast either.

Although I love FPGA and such, I feel that I cannot spend months and months only to make the memory work. Microblaze is nothing I need nor want to use.
I and many others would certainly appreciate any help we can get with this !

[Examples of using the DDR3 on ARTY S7 board]

Hi,

I have this board and need to use DDR3. To my surprise, there are no examples whatsoever of how to use it. I have tried with MIG a couple of months back but was so disappointed about the complexity that I gave up on my project. Now I got some strength to try again.

Why are there no examples of how to use the DDR3 memory on your site?

Regards,
Mathias