[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_gen_inst/inst/clk_in1_clk_gen] >

	clk_gen_inst/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y26
	 clk_gen_inst/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	 clk_gen_inst/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
	 clk_gen_inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

	Clock Rule: rule_mmcm_bufhce
	Status: PASS 
	Rule Description: An MMCM driving a BUFH must both be in the same horizontal row (clockregion-wise)
	 clk_gen_inst/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT2) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
	 clk_gen_inst/inst/clkout3_buf (BUFHCE.I) is provisionally placed by clockplacer on BUFHCE_X1Y7

	Clock Rule: rule_bufh_bufr_ramb
	Status: PASS 
	Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
	than the capacity of the region
	 clk_gen_inst/inst/clkout3_buf (BUFHCE.O) is provisionally placed by clockplacer on BUFHCE_X1Y7

	Clock Rule: rule_bufhce_pll
	Status: PASS 
	Rule Description: A BUFH driving a PLL must both be in the same clock region
	 clk_gen_inst/inst/clkout3_buf (BUFHCE.O) is provisionally placed by clockplacer on BUFHCE_X1Y7
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X1Y0

	Clock Rule: rule_clk_locked_loads
	Status: PASS 
	Rule Description NOT AVAILABLE
	 clk_gen_inst/inst/clkout3_buf (BUFHCE.O) is provisionally placed by clockplacer on BUFHCE_X1Y7
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is locked to PLLE2_ADV_X1Y0

	Clock Rule: rule_pll_bufhce
	Status: PASS 
	Rule Description: A PLL driving a BUFH must both be in the same horizontal row (clockregion-wise)
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKOUT3) is locked to PLLE2_ADV_X1Y0
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y8

	Clock Rule: rule_bufh_bufr_ramb
	Status: PASS 
	Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
	than the capacity of the region
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y8

	Clock Rule: rule_bufhce_mmcm
	Status: PASS 
	Rule Description: A BUFH driving an MMCM must both be in the same clock region
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y8
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKIN1) is locked to MMCME2_ADV_X1Y0

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	 ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKFBOUT) is locked to MMCME2_ADV_X1Y0
	 and ram_inst/u_mem/u_mem_mig/u_ddr3_infrastructure/u_bufg_clkdiv0 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y3