DigbyT

As promised in the original question, this is a summary of the steps I performed to recreate the hardware project for the PetaLinux DEMO.. 1. Install Vivado 2022.1 on Ubuntu 22.04.2 2. Install Digilent board files. Following the instructions in https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis the Master Branch ZIP Archive of Digilent’s Vivado-boards Github repository was downloaded from https://github.com/Digilent/vivado-boards/archive/master.zip?_ga=2.33613281.1549222001.1726043306-390947864.1722385952 and the vivado-boards-master.zip file unpacked in a directory on the build system. As the Xilinx tools being used are newer than 2014.4, the new/board_files directory in the resultant file tree will be used. https://github.com/Digilent/vivado-boards/archive/master.zip?_ga=2.33613281.1549222001.1726043306-390947864.1722385952 and the vivado-boards-master.zip file unpacked in a directory on the build system. As the Xilinx tools being used are newer than 2014.4, the new/board_files directory in the resultant file tree will be used. Next change to the board_files directory and create a board_files directory in the Xilinx tools installation directory $ cd new/board_files $ mkdir ..../Vivado/2022.1/data/boards/board_files $ cp -ar * ..../Vivado/2022.1/data/boards/board_files/ 3. Pull the git repositories Using the instructions found here: https://digilent.com/reference/programmable-logic/documents/git?redirect=1 And browsing repositories listed here: https://github.com/orgs/Digilent/repositories?type=all $ git clone --recursive https://github.com/Digilent/Zybo-Z7 Submodule path 'hw': checked out '89b4a8e5f9f6f1579cb4768a9aeff0f3640093b9' Submodule 'repo/vivado-library' (https://github.com/Digilent/vivado-library.git)\ registered for path 'hw/repo/vivado-library' Submodule 'scripts' (https://github.com/Digilent/digilent-vivado-scripts.git) \ registered for path 'hw/scripts' Cloning into '../work/src/xilinx/zyboz7_demo/demo/Petalinux/gethw/Zybo-Z7/hw/repo/vivado-library'... Cloning into '/home/digbyt/work/src/xilinx/zyboz7_demo/demo/Petalinux/gethw/Zybo-Z7/hw/scripts'... Submodule path 'hw/repo/vivado-library': checked out 'ab565ed50c85eaacb3e8b8fdce67a2a03ae779a4' Submodule path 'hw/scripts': checked out 'ba6bbb948f13805db6172d3e04749671e685c9da' Submodule path 'os': checked out '687e34544ab482e2b8a0a98f0f8653496ca17192' $ cd Zybo-Z7 $ git branch -a * master remotes/origin/10/DMA/master remotes/origin/10/HDMI/master remotes/origin/10/Pcam-5C/master remotes/origin/10/Petalinux/master remotes/origin/10/Pmod-VGA/master remotes/origin/10/XADC/master remotes/origin/20/DMA/master remotes/origin/20/HDMI/master remotes/origin/20/Pcam-5C/master remotes/origin/20/Petalinux/master remotes/origin/20/Pmod-ToF/master remotes/origin/20/Pmod-VGA/master remotes/origin/20/XADC/master remotes/origin/HEAD -> origin/master remotes/origin/master $ git checkout remotes/origin/20/Petalinux/master M hw M os Note: switching to 'remotes/origin/20/Petalinux/master'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c <new-branch-name> Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at 450d614 Advanced os submodule to 2022.1 $ git submodule update --init --recursive Submodule path 'hw': checked out '89b4a8e5f9f6f1579cb4768a9aeff0f3640093b9' Submodule 'repo/vivado-library' (https://github.com/Digilent/vivado-library.git)\ registered for path 'hw/repo/vivado-library' Submodule 'scripts' (https://github.com/Digilent/digilent-vivado-scripts.git) \ registered for path 'hw/scripts' Cloning into '../work/src/xilinx/zyboz7_demo/demo/Petalinux/gethw/Zybo-Z7/hw/repo/vivado-library'... Cloning into '/home/digbyt/work/src/xilinx/zyboz7_demo/demo/Petalinux/gethw/Zybo-Z7/hw/scripts'... Submodule path 'hw/repo/vivado-library': checked out 'ab565ed50c85eaacb3e8b8fdce67a2a03ae779a4' Submodule path 'hw/scripts': checked out 'ba6bbb948f13805db6172d3e04749671e685c9da' Submodule path 'os': checked out '687e34544ab482e2b8a0a98f0f8653496ca17192' 4. Change the part file version numer. As described in the question, Step 5 fails unless the following patch is made.. $ cd .../Vivado/2022.1/data/boards/board_files/zybo-z7-20/A.0 $ vi board.xml $ diff $HOME/board.xml.orig board.xml 29c29 < <file_version>1.2</file_version> --- > <file_version>1.1</file_version> 5. Run Vivado, open the TCL window and run the command: set argv “”; source {local root repo}/hw/scripts/dcheckout.tcl 6. Project is Open in Vivado The end result is shown in the attached image, which looks ok except for the 'critical warnings' produced during the conversion.

I have built and run the PetaLinux demo for Zybo z7-20 using 2022.1 Xilinx tools on Ubuntu 22.04.2 without any problems, but have found it a bit more difficult to find and rebuild to the HW part of the project. I have gotten tantalizingly close, but my remaining issues occur when trying to run the TCL script to recreate the project as described in "Vivado (HW) Projects" in the document "Digilent FPGA Demo Git Repositories". The issues are: 1. The example TCL command seems wrong: the "digilent_vivado_checkout.tcl" does not exist, so I have assumed that "checkout.tcl" is what was meant. 2. The TCL script failes with: # set_project_properties_post_create_project $proj_name ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:zybo-z7-20:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7z020clg400-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store. And no, I had not forgotten to install the part files. But I checked, and it seems the saved project expects an older version that is contained in the current vivado-boards-master.zip. I have digilentinc.com:zybo-z7-20:part0:1.2 when the archived project expects digilentinc.com:zybo-z7-20:part0:1.1. 3. To progress I edited the version number in the relevant part file to say 1.1, and this allowed the restore and open to complete, but there were a number of "Critical Warnings" and other unsettling messages which make me concerned that the 1.2 part file might not be a satisfactory substitute. So, assuming the changed name of the TCL script was just a documentation error/oversight, my question is: Do I need a 1.1 version of the board support file, and if so, where can I find it. If not, are any of the warnings shown below cause for concern? As it took quite a bit of time to work out how to get a buildable project, I will summarise the steps in a follow up message. There were many questions on the procedure in the forum, none of which had answers thich helped me to it to work properly. So it might help others. And it I have made any mistakes, I hope someone will point them out to me. That will also provide detailed information on which files I used. The warnings and errors that I get when running the TCL script with the 1.2 part file are: This allowed the project to be restored (Figure 21), but a few error diagnostics were produced which may have been the result of the mismatch: INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog: xilinx.com:ip:xlslice:* digilentinc.com:ip:axi_dynclk:* xilinx.com:ip:axi_gpio:* digilentinc.com:user:axi_i2s_adi:* xilinx.com:ip:axi_iic:* xilinx.com:ip:axi_vdma:* xilinx.com:ip:axis_subset_converter:* xilinx.com:ip:clk_wiz:* digilentinc.com:ip:dvi2rgb:* xilinx.com:ip:mipi_csi2_rx_subsystem:* xilinx.com:ip:proc_sys_reset:* xilinx.com:ip:processing_system7:* digilentinc.com:IP:PWM:* digilentinc.com:ip:rgb2dvi:* xilinx.com:ip:util_ds_buf:* xilinx.com:ip:v_axi4s_vid_out:* xilinx.com:ip:v_frmbuf_wr:* xilinx.com:ip:v_tc:* xilinx.com:ip:v_vid_in_axi4s:* xilinx.com:ip:xadc_wiz:* xilinx.com:ip:xlconcat:* xilinx.com:ip:xlconstant:* . INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI INFO: [PS7-6] Configuring Board Preset part0. Please wait ...... CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values. INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI INFO: [Device 21-403] Loading part xc7z020clg400-1 CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values. CRITICAL WARNING: [PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values. INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz_0 clk_wiz propagate INFO: [digilentinc.com:ip:axi_dynclk:1.2-17] /axi_dynclk_0FREQ_HZ of 100000000 propagated into CONFIG.kRefClkFreqHz CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /v_frmbuf_wr_0/s_axis_video(3) and /axis_subset_converter_0/M_AXIS(2) CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /v_axi4s_vid_out_0/video_in(3) and /axis_subset_converter_out/M_AXIS(4) WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/s00_couplers/auto_pc/s_axi_arlock'(1) to pin: '/axi_mem_intercon/s00_couplers/S_AXI_arlock'(2) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/s00_couplers/auto_pc/s_axi_awlock'(1) to pin: '/axi_mem_intercon/s00_couplers/S_AXI_awlock'(2) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon_HP0/m00_couplers/m00_regslice/m_axi_rid'(1) to pin: '/axi_mem_intercon_HP0/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon_HP0/m00_couplers/m00_regslice/m_axi_bid'(1) to pin: '/axi_mem_intercon_HP0/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_wid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/v_frmbuf_wr_0/s_axis_video_TDATA'(24) to pin: '/axis_subset_converter_0/m_axis_tdata'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/v_axi4s_vid_out_0/s_axis_video_tdata'(24) to pin: '/axis_subset_converter_out/m_axis_tdata'(32) - Only lower order bits will be connected. VHDL Output written to : /home/digbyt/work/src/xilinx/2020/zybo/Zybo-Z7/hw/proj/hw.gen/sources_1/bd/system/synth/system.vhd WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/s00_couplers/auto_pc/s_axi_arlock'(1) to pin: '/axi_mem_intercon/s00_couplers/S_AXI_arlock'(2) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/s00_couplers/auto_pc/s_axi_awlock'(1) to pin: '/axi_mem_intercon/s00_couplers/S_AXI_awlock'(2) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon_HP0/m00_couplers/m00_regslice/m_axi_rid'(1) to pin: '/axi_mem_intercon_HP0/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon_HP0/m00_couplers/m00_regslice/m_axi_bid'(1) to pin: '/axi_mem_intercon_HP0/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_wid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon_HP0/M00_AXI_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/v_frmbuf_wr_0/s_axis_video_TDATA'(24) to pin: '/axis_subset_converter_0/m_axis_tdata'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/v_axi4s_vid_out_0/s_axis_video_tdata'(24) to pin Thanks, Digby Tarvin.