As a newbie to FPGA, i have been searching for different ways to access the DDR3 RAM on the Arty A7-35 board. The solution seems to be to use MicroBlaze, Vitis or the SDK. My project involves using the VGA PMOD. I would like to create a VGA controller that uses the DDR3 memory as a double buffer.
My question is, if i want to use verilog code to update one of the buffers, how do i do this if i use MicroBlaze but do not want to use vitis (i.e. i want to use vivado).