okonomiyonda

I'm just getting started with FPGAs, Arty, and Zynq, so I apologise if this is a beginner question or what I'm saying doesn't make total sense.
I'm trying to figure out how to read/write DDR and use the UART from the FPGA side with no involvement from the CPU/PS. I've seen Vivado tutorials where you connect the FPGA over AXI and have the CPU sit in a while loop and printf to the UART. I've seen Vivado tutorials where the CPU sits in a while loop, waits for AXI data or interrupts from the FPGA, reads data from memory, flushes the cache, and sends the data to the FPGA. What I can't seem to find is any examples of the FPGA directly talking to DDR and UART.
What I know so far:
Starting with the image here, it looks like the PL side should be able to talk to DDR and UART over the AMBA interconnect through AXI ports. And indeed, the docs say "cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory" which at least makes me think DDR should be accessible to the FPGA via AXI DMA without PS involvement. I just can't find an example of what I need to do in Vivado to get this hooked up. Separate question: It looks like the PS has a direct connection to DDR that doesn't go over AMBA, so I am wondering what has priority in DDR access, and what the approximate order of magnitude speed difference between CPU uncached direct access and AXI DMA access from the FPGA would be.
Maybe the picture is different for the UART, where I see "the peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space". Again, it looks like both the PL and peripherals are connected to the AMBA interconnect, albeit both as slaves. It also seems that peripheral control registers are only accessible in the processes memory space, but if I can rely on the default reset values, maybe that's not a problem?
So the TL;DR version is Is it possible to read and write DDR from the FPGA without PS involvement? Can I use the UART from the FPGA without PS involvement? Are there any good samples out there I could reference?