Is the "Data Gen" block a known good AXI/DMA block, or something that is under development?
If it is under development, the story below may be relevant.
I have implemented PL-PS on various Digilent boards and did have to use ILA to get the signalling right.
My problems were at the PL side, specifically the Valid and Ready signals. Essentially the Slave can deassert Ready at ~anytime, including while the Master is clocking data, hence the Master needs to test Ready after clocking and may need to reclock same data multiple times, else the transfer will come up short on data. The diagram below is something I found, and similar diagrams are in the Xilinx documents. See the (3) and (5) cases in the below - where D0 and D3 are clocked multiple times:
For my work, the Ready being deasserted situation was not a problem with small packets, but became a barrier for larger packets, maybe related to FIFO size.
Dave
aadgl got a reaction from RyanW in AXI DMA Help on Cora Z7-10