Mukul
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Hello everyone
I'm designing asynchronous FIFO using different styles and want to know how to do latency and throughput analysis of my design.
I need to determine latency and throughput values for each design and don't know how to do so.
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Hi @D@n
If throughput is one value per the speed of slower clock then it is same for all design, that is not true.
I read somewhere that throughput is (frequency*input)/ latency.
And same for latency, it should be different for every design.
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