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@jpeyron that of good help,sir..But one thing just i want to know that suppose i have 40 analog inputs. Can i feed them ( after converting them to digital inputs by ADC pmods) to zedboard FPGA through the FMC?? Since its showing that the FMC LPC has 68 single ended digital i/o.

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All of the FMC LAxxx signals can be inputs. The two FMC_CLKx signal pairs can also be inputs though they are intended for clock inputs. 68 pins spread across 40 ADCs implies that you want to have less than 2 pins per ADC interface. I don't know of any ADC devices with one interface pin. I suppose that if your ADCs have 1 CLK input and 1 data output you could multiplex the pins or try to drive multiple ADC CLKs from 1 FPGA pin. 40 loads on a clock source is going to be problematic even if you have excellent PCB signal integrity. The bigger problem is that you will have to make up some kind of custom FMC mezzanine board to connect all of those ADCs. If I had to do that I'd just design my own 40 channel ADC board. Making such a board in quantities of one or two won't be cheap. The FMC connectors aren't cheap either and can't be hand soldered as they are all SMT form factors.

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Hi @sourav,

What sampling rate do you need for your analog signals? What kind of ADCs do you plan to use?

As @zygot says, you do not have enough pins for 40 parallel ADC connections, but if your required sampling rate is low enough you can multiplex the digitized data on a smaller number of pins. If the sampling rate is too high you might need to use a bigger FPGA.



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I don't know if any of the FMC pins connect to XADC, so pretty much all the signal pins are digital.  Some are capable of differential signaling and some are routed for clocks.

The reason I suggest the schematics rather than the FMC spec is that it depends on what kind of FPGA pin the FMC connector pin is connected to. According to the FMC spec, LAXY_P and LAXY_N would be a differential pair, but they might not be connected to a differential capable pair of pins on the Zedboard.

Furthermore, it's safest to develop basic FPGA logic and provide an xdc constraint file with the desired pinout and ensure that Vivado can place and route your design with the desired pinout before you build a PCB with an FMC connector.

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